<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27130">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/sb: Fix non-local header treated as local<br><br>Change-Id: I4b9bcb74b6441db9e44fe471b9cd789e42e7093a<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/bd82x6x/early_pch.c<br>M src/southbridge/intel/bd82x6x/early_rcba.c<br>M src/southbridge/intel/bd82x6x/early_usb.c<br>M src/southbridge/intel/ibexpeak/smihandler.c<br>4 files changed, 4 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27130/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c</span><br><span>index 427e58c..498480a 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_pch.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_pch.c</span><br><span>@@ -13,7 +13,6 @@</span><br><span>  * GNU General Public License for more details.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span> #include <string.h></span><br><span> #include <arch/io.h></span><br><span> #include <cbmem.h></span><br><span>@@ -27,7 +26,7 @@</span><br><span> #include <southbridge/intel/common/rcba.h></span><br><span> #include "pch.h"</span><br><span> /* For DMI bar.  */</span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> </span><br><span> #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>index 9ce9dc9..9673f28 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_rcba.c</span><br><span>@@ -18,7 +18,7 @@</span><br><span> #include <stdint.h></span><br><span> #include "pch.h"</span><br><span> #include <southbridge/intel/common/rcba.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/sandybridge.h></span><br><span> </span><br><span> void</span><br><span> southbridge_configure_default_intmap(void)</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c</span><br><span>index a036858..8df4a00 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/early_usb.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/early_usb.c</span><br><span>@@ -15,10 +15,9 @@</span><br><span>  */</span><br><span> </span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include <device/pci_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE.  */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE.  */</span><br><span> #include "pch.h"</span><br><span> </span><br><span> void</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>index 12a7ac0..d920ef7 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/smihandler.c</span><br><span>@@ -32,7 +32,7 @@</span><br><span>  *  1. the chipset can do it</span><br><span>  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge/intel/nehalem/nehalem.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/nehalem/nehalem.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <arch/io.h></span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27130">change 27130</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27130"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4b9bcb74b6441db9e44fe471b9cd789e42e7093a </div>
<div style="display:none"> Gerrit-Change-Number: 27130 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>