[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmem
Richard Spiegel (Code Review)
gerrit at coreboot.org
Thu Jun 14 23:58:10 CEST 2018
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27109
Change subject: soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmem
......................................................................
soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmem
PM registers used for generating SWS values are being stored in a static
variable within southbridge.c. In order to have it available for any source
involved in building the platform, move the storage to cbmem, using id
CBMEM_ID_POWER_STATE. Also add a variable that informs from which state
the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This
variable will later be useful in detecting failed S3 resume.
BUG=b:80119811
TEST=Add code to print SWS parameters and state it's waking from. Build
and boot grunt, suspend and resume, check output for valid values. Remove
the print code.
Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
2 files changed, 28 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/27109/1
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 1750547..40cf621 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -68,6 +68,8 @@
#define GBL_EN BIT(5)
#define TIMER_STS BIT(0)
#define PM1_CNT_BLK 0x62
+#define PM1_WAKE_SHIFT 10
+#define PM1_WAKE_MASK (7 << PM1_WAKE_SHIFT)
#define PM_TMR_BLK 0x64
#define PM_CPU_CTRL 0x66
#define PM_GPE0_BLK 0x68
@@ -361,6 +363,14 @@
int status;
};
+struct soc_power_reg {
+ uint16_t pm1_sts;
+ uint16_t pm1_en;
+ uint32_t gpe0_sts;
+ uint32_t gpe0_en;
+ uint16_t wake_from;
+};
+
void enable_aoac_devices(void);
void sb_enable_rom(void);
void configure_stoneyridge_i2c(void);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 02daa260..0f69e5b 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -662,25 +662,24 @@
elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
}
-struct soc_amd_sws {
- uint16_t pm1_sts;
- uint16_t pm1_en;
- uint32_t gpe0_sts;
- uint32_t gpe0_en;
-};
-
-static struct soc_amd_sws sws;
-
static void sb_save_sws(uint16_t pm1_status)
{
+ struct soc_power_reg *sws;
uint32_t reg32;
+ uint16_t reg16;
- sws.pm1_sts = pm1_status;
- sws.pm1_en = inw(ACPI_PM1_EN);
+ sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg));
+ if (sws == NULL)
+ return;
+ sws->pm1_sts = pm1_status;
+ sws->pm1_en = inw(ACPI_PM1_EN);
reg32 = inl(ACPI_GPE0_STS);
outl(ACPI_GPE0_STS, reg32);
- sws.gpe0_sts = reg32;
- sws.gpe0_en = inl(ACPI_GPE0_EN);
+ sws->gpe0_sts = reg32;
+ sws->gpe0_en = inl(ACPI_GPE0_EN);
+ reg16 = inw(ACPI_PM1_CNT_BLK);
+ reg16 &= PM1_WAKE_MASK;
+ sws->wake_from = reg16 >> PM1_WAKE_SHIFT;
}
static void sb_clear_pm1_status(void)
@@ -715,20 +714,24 @@
static void set_nvs_sws(void *unused)
{
+ struct soc_power_reg *sws;
struct global_nvs_t *gnvs;
int index;
+ sws = cbmem_find(CBMEM_ID_POWER_STATE);
+ if (sws == NULL)
+ return;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs == NULL)
return;
- index = get_index_bit(sws.pm1_sts & sws.pm1_en, PM1_LIMIT);
+ index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT);
if (index < 0)
gnvs->pm1i = ~0ULL;
else
gnvs->pm1i = index;
- index = get_index_bit(sws.gpe0_sts & sws.gpe0_en, GPE0_LIMIT);
+ index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT);
if (index < 0)
gnvs->gpei = ~0ULL;
else
--
To view, visit https://review.coreboot.org/27109
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986
Gerrit-Change-Number: 27109
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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