<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27109">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmem<br><br>PM registers used for generating SWS values are being stored in a static<br>variable within southbridge.c. In order to have it available for any source<br>involved in building the platform, move the storage to cbmem, using id<br>CBMEM_ID_POWER_STATE. Also add a variable that informs from which state<br>the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This<br>variable will later be useful in detecting failed S3 resume.<br><br>BUG=b:80119811<br>TEST=Add code to print SWS parameters and state it's waking from. Build<br>and boot grunt, suspend and resume, check output for valid values. Remove<br>the print code.<br><br>Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 28 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/27109/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 1750547..40cf621 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -68,6 +68,8 @@</span><br><span> #define GBL_EN BIT(5)</span><br><span> #define TIMER_STS BIT(0)</span><br><span> #define PM1_CNT_BLK 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM1_WAKE_SHIFT 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM1_WAKE_MASK (7 << PM1_WAKE_SHIFT)</span><br><span> #define PM_TMR_BLK 0x64</span><br><span> #define PM_CPU_CTRL 0x66</span><br><span> #define PM_GPE0_BLK 0x68</span><br><span>@@ -361,6 +363,14 @@</span><br><span> int status;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_power_reg {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t pm1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t pm1_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t wake_from;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void enable_aoac_devices(void);</span><br><span> void sb_enable_rom(void);</span><br><span> void configure_stoneyridge_i2c(void);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 02daa260..0f69e5b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -662,25 +662,24 @@</span><br><span> elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-struct soc_amd_sws {</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t pm1_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t pm1_en;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_en;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct soc_amd_sws sws;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void sb_save_sws(uint16_t pm1_status)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct soc_power_reg *sws;</span><br><span> uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t reg16;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- sws.pm1_sts = pm1_status;</span><br><span style="color: hsl(0, 100%, 40%);">- sws.pm1_en = inw(ACPI_PM1_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sws == NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ sws->pm1_sts = pm1_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ sws->pm1_en = inw(ACPI_PM1_EN);</span><br><span> reg32 = inl(ACPI_GPE0_STS);</span><br><span> outl(ACPI_GPE0_STS, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">- sws.gpe0_sts = reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- sws.gpe0_en = inl(ACPI_GPE0_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ sws->gpe0_sts = reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ sws->gpe0_en = inl(ACPI_GPE0_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = inw(ACPI_PM1_CNT_BLK);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 &= PM1_WAKE_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ sws->wake_from = reg16 >> PM1_WAKE_SHIFT;</span><br><span> }</span><br><span> </span><br><span> static void sb_clear_pm1_status(void)</span><br><span>@@ -715,20 +714,24 @@</span><br><span> </span><br><span> static void set_nvs_sws(void *unused)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct soc_power_reg *sws;</span><br><span> struct global_nvs_t *gnvs;</span><br><span> int index;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ sws = cbmem_find(CBMEM_ID_POWER_STATE);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sws == NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span> gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);</span><br><span> if (gnvs == NULL)</span><br><span> return;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- index = get_index_bit(sws.pm1_sts & sws.pm1_en, PM1_LIMIT);</span><br><span style="color: hsl(120, 100%, 40%);">+ index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT);</span><br><span> if (index < 0)</span><br><span> gnvs->pm1i = ~0ULL;</span><br><span> else</span><br><span> gnvs->pm1i = index;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- index = get_index_bit(sws.gpe0_sts & sws.gpe0_en, GPE0_LIMIT);</span><br><span style="color: hsl(120, 100%, 40%);">+ index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT);</span><br><span> if (index < 0)</span><br><span> gnvs->gpei = ~0ULL;</span><br><span> else</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27109">change 27109</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986 </div>
<div style="display:none"> Gerrit-Change-Number: 27109 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>