[coreboot-gerrit] Change in coreboot[master]: src: Get rid of unneeded whitespace

Wed Jun 13 12:13:06 CEST 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 )

Change subject: src: Get rid of unneeded whitespace
......................................................................

Patch Set 14:

(21 comments)

https://review.coreboot.org/#/c/26991/14/src/include/bootstate.h
File src/include/bootstate.h:

https://review.coreboot.org/#/c/26991/14/src/include/bootstate.h@127
PS14, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_)			\
Single statement macros should not use a do {} while (0) loop

https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/bimini_fam10/romstage.c
File src/mainboard/amd/bimini_fam10/romstage.c:

https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/bimini_fam10/romstage.c@83
PS14, Line 83: 		inb(0x80);	/* Wait sometime before post to port80, otherwise reset was needed. */
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/tilapia_fam10/mainboard.c
File src/mainboard/amd/tilapia_fam10/mainboard.c:

https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/tilapia_fam10/mainboard.c@153
PS14, Line 153: 		/* When the gpio40 is configured as GPIO, this will represent the output value*/
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/tilapia_fam10/mainboard.c@165
PS14, Line 165: 		/* When the gpio40 is configured as GPIO, this will represent the output value*/
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/mainboard/asus/kfsn4-dre/resourcemap.c
File src/mainboard/asus/kfsn4-dre/resourcemap.c:

https://review.coreboot.org/#/c/26991/14/src/mainboard/asus/kfsn4-dre/resourcemap.c@229
PS14, Line 229: //		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/mainboard/tyan/s2912_fam10/resourcemap.c
File src/mainboard/tyan/s2912_fam10/resourcemap.c:

https://review.coreboot.org/#/c/26991/14/src/mainboard/tyan/s2912_fam10/resourcemap.c@269
PS14, Line 269: //		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55	*/
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/agesa/family14/chip.h
File src/northbridge/amd/agesa/family14/chip.h:

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/agesa/family14/chip.h@30
PS14, Line 30: 	 *	{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdht/h3gtopo.h
File src/northbridge/amd/amdht/h3gtopo.h:

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdht/h3gtopo.h@259
PS14, Line 259: 	0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF	// Node6
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct/mctdqs_d.c
File src/northbridge/amd/amdmct/mct/mctdqs_d.c:

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct/mctdqs_d.c@464
PS14, Line 464: 		BanksPresent = 1;	/* flag for at least one bank is present */
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c:

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@118
PS14, Line 118: 	OB_ChipKill = mctGet_NVbits(NV_ChipKill);		/* ECC Chip-kill mode */
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@123
PS14, Line 123: 		/* mct_AdjustScrub_D(pDCTstatA, &nvbits); */	/* Need not adjust */
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:

https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@710
PS14, Line 710: 			//	wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c
File src/southbridge/amd/cimx/sb800/late.c:

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c@355
PS14, Line 355: 			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c@361
PS14, Line 361: 			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c@390
PS14, Line 390: 			if (AZALIA_DISABLE == sb_config->AzaliaController) {
Comparisons should place the constant on the right side of the test

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c@390
PS14, Line 390: 			if (AZALIA_DISABLE == sb_config->AzaliaController) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb900/late.c
File src/southbridge/amd/cimx/sb900/late.c:

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb900/late.c@383
PS14, Line 383: 			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb900/late.c@390
PS14, Line 390: 			if (sb_config->AzaliaController == AZALIA_DISABLE) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/gfx.c
File src/southbridge/amd/rs780/gfx.c:

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/gfx.c@452
PS14, Line 452: 	vgainfo.ulBootUpEngineClock = 500 * 100;		// setup option on reference BIOS, 500 is default
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/rs780.c
File src/southbridge/amd/rs780/rs780.c:

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/rs780.c@96
PS14, Line 96: 	/* CLKCFG:0xE8 Bit[17] = 0x1	 Powerdown clock to IOC GFX block in no external graphics mode */
line over 80 characters

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/sr5650/cmn.h
File src/southbridge/amd/sr5650/cmn.h:

https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/sr5650/cmn.h@23
PS14, Line 23: #define NBHTIU_INDEX	0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
line over 80 characters

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Gerrit-Change-Number: 26991
Gerrit-PatchSet: 14
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Wed, 13 Jun 2018 10:13:06 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: No
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