<p><a href="https://review.coreboot.org/26991">View Change</a></p><p>21 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/include/bootstate.h">File src/include/bootstate.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/include/bootstate.h@127">Patch Set #14, Line 127:</a> <code style="font-family:monospace,monospace">#define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Single statement macros should not use a do {} while (0) loop</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/bimini_fam10/romstage.c">File src/mainboard/amd/bimini_fam10/romstage.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/bimini_fam10/romstage.c@83">Patch Set #14, Line 83:</a> <code style="font-family:monospace,monospace"> inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/tilapia_fam10/mainboard.c">File src/mainboard/amd/tilapia_fam10/mainboard.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/tilapia_fam10/mainboard.c@153">Patch Set #14, Line 153:</a> <code style="font-family:monospace,monospace"> /* When the gpio40 is configured as GPIO, this will represent the output value*/</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/mainboard/amd/tilapia_fam10/mainboard.c@165">Patch Set #14, Line 165:</a> <code style="font-family:monospace,monospace"> /* When the gpio40 is configured as GPIO, this will represent the output value*/</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/mainboard/asus/kfsn4-dre/resourcemap.c">File src/mainboard/asus/kfsn4-dre/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/mainboard/asus/kfsn4-dre/resourcemap.c@229">Patch Set #14, Line 229:</a> <code style="font-family:monospace,monospace">// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/mainboard/tyan/s2912_fam10/resourcemap.c">File src/mainboard/tyan/s2912_fam10/resourcemap.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/mainboard/tyan/s2912_fam10/resourcemap.c@269">Patch Set #14, Line 269:</a> <code style="font-family:monospace,monospace">// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/agesa/family14/chip.h">File src/northbridge/amd/agesa/family14/chip.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/agesa/family14/chip.h@30">Patch Set #14, Line 30:</a> <code style="font-family:monospace,monospace"> * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdht/h3gtopo.h">File src/northbridge/amd/amdht/h3gtopo.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdht/h3gtopo.h@259">Patch Set #14, Line 259:</a> <code style="font-family:monospace,monospace"> 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct/mctdqs_d.c">File src/northbridge/amd/amdmct/mct/mctdqs_d.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct/mctdqs_d.c@464">Patch Set #14, Line 464:</a> <code style="font-family:monospace,monospace"> BanksPresent = 1; /* flag for at least one bank is present */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c">File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@118">Patch Set #14, Line 118:</a> <code style="font-family:monospace,monospace"> OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@123">Patch Set #14, Line 123:</a> <code style="font-family:monospace,monospace"> /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c">File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@710">Patch Set #14, Line 710:</a> <code style="font-family:monospace,monospace"> // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c">File src/southbridge/amd/cimx/sb800/late.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c@355">Patch Set #14, Line 355:</a> <code style="font-family:monospace,monospace"> sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c@361">Patch Set #14, Line 361:</a> <code style="font-family:monospace,monospace"> sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c@390">Patch Set #14, Line 390:</a> <code style="font-family:monospace,monospace"> if (AZALIA_DISABLE == sb_config->AzaliaController) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Comparisons should place the constant on the right side of the test</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb800/late.c@390">Patch Set #14, Line 390:</a> <code style="font-family:monospace,monospace"> if (AZALIA_DISABLE == sb_config->AzaliaController) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb900/late.c">File src/southbridge/amd/cimx/sb900/late.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb900/late.c@383">Patch Set #14, Line 383:</a> <code style="font-family:monospace,monospace"> sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/cimx/sb900/late.c@390">Patch Set #14, Line 390:</a> <code style="font-family:monospace,monospace"> if (sb_config->AzaliaController == AZALIA_DISABLE) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/gfx.c">File src/southbridge/amd/rs780/gfx.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/gfx.c@452">Patch Set #14, Line 452:</a> <code style="font-family:monospace,monospace"> vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/rs780.c">File src/southbridge/amd/rs780/rs780.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/rs780/rs780.c@96">Patch Set #14, Line 96:</a> <code style="font-family:monospace,monospace"> /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/sr5650/cmn.h">File src/southbridge/amd/sr5650/cmn.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/26991/14/src/southbridge/amd/sr5650/cmn.h@23">Patch Set #14, Line 23:</a> <code style="font-family:monospace,monospace">#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/26991">change 26991</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26991"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da </div>
<div style="display:none"> Gerrit-Change-Number: 26991 </div>
<div style="display:none"> Gerrit-PatchSet: 14 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Wed, 13 Jun 2018 10:13:06 +0000 </div>
<div style="display:none"> Gerrit-HasComments: Yes </div>
<div style="display:none"> Gerrit-HasLabels: No </div>