[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801xx: Use common RCBA MACROs

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27043


Change subject: sb/intel/i82801xx: Use common RCBA MACROs
......................................................................

sb/intel/i82801xx: Use common RCBA MACROs

Change-Id: I61fb3b01ff15ba2da2ee938addfa630c282c9870
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/i82801gx/i82801gx.h
M src/southbridge/intel/i82801ix/i82801ix.h
M src/southbridge/intel/i82801jx/i82801jx.h
3 files changed, 3 insertions(+), 29 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27043/1

diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 36c79eb..d14a809 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -31,11 +31,7 @@
 #define DEFAULT_GPIOBASE	0x0480
 #define DEFAULT_PMBASE		0x0500
 
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+#include <southbridge/intel/common/rcba.h>
 
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
@@ -194,10 +190,6 @@
 /* Root Complex Register Block */
 #define RCBA		0xf0
 
-#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + (x))))
-#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x))))
-#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + (x))))
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 38dfa38..2bce3ab 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -24,12 +24,7 @@
 #endif
 #endif
 
-#define DEFAULT_TBAR		((u8 *)0xfed1b000)
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+#include <southbridge/intel/common/rcba.h>
 
 #if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35)
 /*
@@ -154,10 +149,6 @@
 #define SMB_SMI_EN		(1 << 1)
 #define HST_EN			(1 << 0)
 
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
 #define RCBA_V0CTL		0x0014
 #define RCBA_V1CAP		0x001c
 #define RCBA_V1CTL		0x0020
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 88e0ad0..1e63e4f 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -24,12 +24,7 @@
 #endif
 #endif
 
-#define DEFAULT_TBAR		((u8 *)0xfed1b000)
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+#include <southbridge/intel/common/rcba.h>
 
 #define DEFAULT_PMBASE		0x00000500
 #define DEFAULT_TCOBASE		(DEFAULT_PMBASE + 0x60)
@@ -147,10 +142,6 @@
 #define SMB_SMI_EN		(1 << 1)
 #define HST_EN			(1 << 0)
 
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
 #define RCBA_V0CTL		0x0014
 #define RCBA_V1CAP		0x001c
 #define RCBA_V1CTL		0x0020

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I61fb3b01ff15ba2da2ee938addfa630c282c9870
Gerrit-Change-Number: 27043
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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