<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27043">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801xx: Use common RCBA MACROs<br><br>Change-Id: I61fb3b01ff15ba2da2ee938addfa630c282c9870<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/southbridge/intel/i82801gx/i82801gx.h<br>M src/southbridge/intel/i82801ix/i82801ix.h<br>M src/southbridge/intel/i82801jx/i82801jx.h<br>3 files changed, 3 insertions(+), 29 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27043/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>index 36c79eb..d14a809 100644</span><br><span>--- a/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>+++ b/src/southbridge/intel/i82801gx/i82801gx.h</span><br><span>@@ -31,11 +31,7 @@</span><br><span> #define DEFAULT_GPIOBASE    0x0480</span><br><span> #define DEFAULT_PMBASE                0x0500</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA          ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA             0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span>@@ -194,10 +190,6 @@</span><br><span> /* Root Complex Register Block */</span><br><span> #define RCBA         0xf0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + (x))))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x))))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + (x))))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define VCH          0x0000  /* 32bit */</span><br><span> #define VCAP1            0x0004  /* 32bit */</span><br><span> #define VCAP2            0x0008  /* 32bit */</span><br><span>diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h</span><br><span>index 38dfa38..2bce3ab 100644</span><br><span>--- a/src/southbridge/intel/i82801ix/i82801ix.h</span><br><span>+++ b/src/southbridge/intel/i82801ix/i82801ix.h</span><br><span>@@ -24,12 +24,7 @@</span><br><span> #endif</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_TBAR           ((u8 *)0xfed1b000)</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA          ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA             0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35)</span><br><span> /*</span><br><span>@@ -154,10 +149,6 @@</span><br><span> #define SMB_SMI_EN                (1 << 1)</span><br><span> #define HST_EN                        (1 << 0)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define RCBA_V0CTL             0x0014</span><br><span> #define RCBA_V1CAP            0x001c</span><br><span> #define RCBA_V1CTL            0x0020</span><br><span>diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>index 88e0ad0..1e63e4f 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>+++ b/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>@@ -24,12 +24,7 @@</span><br><span> #endif</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_TBAR                ((u8 *)0xfed1b000)</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA          ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA             0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #define DEFAULT_PMBASE                0x00000500</span><br><span> #define DEFAULT_TCOBASE           (DEFAULT_PMBASE + 0x60)</span><br><span>@@ -147,10 +142,6 @@</span><br><span> #define SMB_SMI_EN            (1 << 1)</span><br><span> #define HST_EN                        (1 << 0)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define RCBA_V0CTL             0x0014</span><br><span> #define RCBA_V1CAP            0x001c</span><br><span> #define RCBA_V1CTL            0x0020</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27043">change 27043</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27043"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I61fb3b01ff15ba2da2ee938addfa630c282c9870 </div>
<div style="display:none"> Gerrit-Change-Number: 27043 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>