[coreboot-gerrit] Change in coreboot[master]: sb/intel/common: Make RCBA manipulation MACROs common

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27041


Change subject: sb/intel/common: Make RCBA manipulation MACROs common
......................................................................

sb/intel/common: Make RCBA manipulation MACROs common

No Change in BUILD_TIMELESS.

Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/bd82x6x/pch.h
A src/southbridge/intel/common/rcba.h
M src/southbridge/intel/ibexpeak/pch.h
3 files changed, 50 insertions(+), 32 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27041/1

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 3975d0c..7c7e0ed 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -45,11 +45,7 @@
 #define DEFAULT_GPIOBASE	0x0480
 #define DEFAULT_PMBASE		0x0500
 
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+#include <southbridge/intel/common/rcba.h>
 
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)
 #define CROS_GPIO_DEVICE_NAME	"CougarPoint"
@@ -270,17 +266,6 @@
 /* Root Complex Register Block */
 #define RCBA		0xf0
 
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
-#define RCBA_AND_OR(bits, x, and, or) \
-        RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
-#define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */
diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h
new file mode 100644
index 0000000..21329a3
--- /dev/null
+++ b/src/southbridge/intel/common/rcba.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
+#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
+
+/*
+ * The DnnIR registers use common RCBA offsets across these chipsets:
+ * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint
+ *
+ * However not all registers are in use on all of these.
+ */
+
+#ifndef __ACPI__
+#define DEFAULT_RCBA		((u8 *)0xfed1c000)
+#else
+#define DEFAULT_RCBA	        0xfed1c000
+#endif
+
+#ifndef __ACPI__
+
+#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))
+#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))
+#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))
+
+#define RCBA_AND_OR(bits, x, and, or) \
+	(RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))
+#define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
+
+
+#endif /* __ACPI__ */
+#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 8012a75..55478b9 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -46,11 +46,7 @@
 #define DEFAULT_GPIOBASE	0x0480
 #define DEFAULT_PMBASE		0x0500
 
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+#include <southbridge/intel/common/rcba.h>
 
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
@@ -242,17 +238,6 @@
 /* Root Complex Register Block */
 #define RCBA		0xf0
 
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
-#define RCBA_AND_OR(bits, x, and, or) \
-        RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
-#define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d
Gerrit-Change-Number: 27041
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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