<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27041">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/common: Make RCBA manipulation MACROs common<br><br>No Change in BUILD_TIMELESS.<br><br>Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/southbridge/intel/bd82x6x/pch.h<br>A src/southbridge/intel/common/rcba.h<br>M src/southbridge/intel/ibexpeak/pch.h<br>3 files changed, 50 insertions(+), 32 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27041/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index 3975d0c..7c7e0ed 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -45,11 +45,7 @@</span><br><span> #define DEFAULT_GPIOBASE 0x0480</span><br><span> #define DEFAULT_PMBASE 0x0500</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)</span><br><span> #define CROS_GPIO_DEVICE_NAME "CougarPoint"</span><br><span>@@ -270,17 +266,6 @@</span><br><span> /* Root Complex Register Block */</span><br><span> #define RCBA 0xf0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define VCH 0x0000 /* 32bit */</span><br><span> #define VCAP1 0x0004 /* 32bit */</span><br><span> #define VCAP2 0x0008 /* 32bit */</span><br><span>diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h</span><br><span>new file mode 100644</span><br><span>index 0000000..21329a3</span><br><span>--- /dev/null</span><br><span>+++ b/src/southbridge/intel/common/rcba.h</span><br><span>@@ -0,0 +1,48 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The DnnIR registers use common RCBA offsets across these chipsets:</span><br><span style="color: hsl(120, 100%, 40%);">+ * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * However not all registers are in use on all of these.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(120, 100%, 40%);">+ (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __ACPI__ */</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>index 8012a75..55478b9 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/pch.h</span><br><span>+++ b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>@@ -46,11 +46,7 @@</span><br><span> #define DEFAULT_GPIOBASE 0x0480</span><br><span> #define DEFAULT_PMBASE 0x0500</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA ((u8 *)0xfed1c000)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEFAULT_RCBA 0xfed1c000</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/rcba.h></span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span> #define DEBUG_PERIODIC_SMIS 0</span><br><span>@@ -242,17 +238,6 @@</span><br><span> /* Root Complex Register Block */</span><br><span> #define RCBA 0xf0</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA_AND_OR(bits, x, and, or) \</span><br><span style="color: hsl(0, 100%, 40%);">- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define VCH 0x0000 /* 32bit */</span><br><span> #define VCAP1 0x0004 /* 32bit */</span><br><span> #define VCAP2 0x0008 /* 32bit */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27041">change 27041</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27041"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d </div>
<div style="display:none"> Gerrit-Change-Number: 27041 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>