[coreboot-gerrit] Change in coreboot[master]: [TEST/NOTFORMERGE]nb/intel/x4x: Use C_ENVIRONMENT_BOOTBLOCK
Arthur Heymans (Code Review)
gerrit at coreboot.org
Tue Jun 12 17:16:03 CEST 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27032
Change subject: [TEST/NOTFORMERGE]nb/intel/x4x: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
[TEST/NOTFORMERGE]nb/intel/x4x: Use C_ENVIRONMENT_BOOTBLOCK
TODO: clean things up.
Tested on Intel DG41WV and it works!
Change-Id: I8984d430a92182ecbabf7e97e054e5550d4fde66
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/car/bootblock.c
M src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S
A src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S
M src/cpu/intel/socket_LGA775/Kconfig
M src/cpu/intel/socket_LGA775/Makefile.inc
M src/mainboard/intel/dg41wv/Makefile.inc
A src/mainboard/intel/dg41wv/bootblock.c
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/Makefile.inc
A src/northbridge/intel/x4x/bootblock_gcc.c
M src/southbridge/intel/i82801gx/Makefile.inc
A src/southbridge/intel/i82801gx/bootblock_gcc.c
M src/superio/winbond/Makefile.inc
M src/superio/winbond/w83627dhg/Makefile.inc
14 files changed, 521 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/27032/1
diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c
index e64073a..7fda5e5 100644
--- a/src/cpu/intel/car/bootblock.c
+++ b/src/cpu/intel/car/bootblock.c
@@ -32,6 +32,8 @@
set_var_mtrr(mtrr, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
}
+__weak void bootblock_early_cpu_init(void) { }
+
void bootblock_soc_early_init(void)
{
bootblock_early_cpu_init();
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S b/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S
index 1c3b736..32ec717 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S
@@ -173,7 +173,6 @@
before_romstage:
post_code(0x29)
- /* Call romstage.c main function. */
call bootblock_c_entry
/* Should never see this postcode */
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S b/src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S
new file mode 100644
index 0000000..351f98c
--- /dev/null
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram_bootblock.S
@@ -0,0 +1,362 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+#include <cpu/x86/lapic_def.h>
+
+/* Macro to access Local APIC registers at default base. */
+#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
+#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff)
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+.global bootblock_pre_c_entry
+
+
+.code32
+bootblock_pre_c_entry:
+_cache_as_ram_setup:
+
+cache_as_ram:
+ post_code(0x20)
+
+ movl $LAPIC_BASE_MSR, %ecx
+ rdmsr
+ andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax
+ jz ap_init
+
+ /* Clear/disable fixed MTRRs */
+ mov $fixed_mtrr_list_size, %ebx
+ xor %eax, %eax
+ xor %edx, %edx
+
+clear_fixed_mtrr:
+ add $-2, %ebx
+ movzwl fixed_mtrr_list(%ebx), %ecx
+ wrmsr
+ jnz clear_fixed_mtrr
+
+ /* Figure put how many MTRRs we have, and clear them out */
+ mov $MTRR_CAP_MSR, %ecx
+ rdmsr
+ movzb %al, %ebx /* Number of variable MTRRs */
+ mov $MTRR_PHYS_BASE(0), %ecx
+ xor %eax, %eax
+ xor %edx, %edx
+
+clear_var_mtrr:
+ wrmsr
+ inc %ecx
+ wrmsr
+ inc %ecx
+ dec %ebx
+ jnz clear_var_mtrr
+ post_code(0x21)
+
+ /* Configure the default memory type to uncacheable. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ andl $(~0x00000cff), %eax
+ wrmsr
+
+ post_code(0x22)
+
+ /* Determine CPU_ADDR_BITS and load PHYSMASK high
+ * word to %edx.
+ */
+ movl $0x80000000, %eax
+ cpuid
+ cmpl $0x80000008, %eax
+ jc addrsize_no_MSR
+ movl $0x80000008, %eax
+ cpuid
+ movb %al, %cl
+ sub $32, %cl
+ movl $1, %edx
+ shl %cl, %edx
+ subl $1, %edx
+ jmp addrsize_set_high
+addrsize_no_MSR:
+ movl $1, %eax
+ cpuid
+ andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */
+ jz addrsize_set_high
+ movl $0x0f, %edx
+
+ /* Preload high word of address mask (in %edx) for Variable
+ * MTRRs 0 and 1 and enable local APIC at default base.
+ */
+addrsize_set_high:
+ xorl %eax, %eax
+ movl $MTRR_PHYS_MASK(0), %ecx
+ wrmsr
+ movl $LAPIC_BASE_MSR, %ecx
+ not %edx
+ movl %edx, %ebx
+ rdmsr
+ andl %ebx, %edx
+ andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax
+ orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax
+ wrmsr
+
+bsp_init:
+
+ post_code(0x23)
+
+ /* Send INIT IPI to all excluding ourself. */
+ movl LAPIC(ICR), %edi
+ movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
+1: movl %eax, (%edi)
+ movl $0x30, %ecx
+2: pause
+ dec %ecx
+ jnz 2b
+ movl (%edi), %ecx
+ andl $LAPIC_ICR_BUSY, %ecx
+ jnz 1b
+
+ post_code(0x24)
+
+ movl $1, %eax
+ cpuid
+ btl $28, %edx
+ jnc sipi_complete
+ bswapl %ebx
+ movzx %bh, %edi
+ cmpb $1, %bh
+ jbe sipi_complete /* only one LAPIC ID in package */
+
+ movl $0, %eax
+ cpuid
+ movb $1, %bl
+ cmpl $4, %eax
+ jb cores_counted
+ movl $4, %eax
+ movl $0, %ecx
+ cpuid
+ shr $26, %eax
+ movb %al, %bl
+ inc %bl
+
+cores_counted:
+ movl %edi, %eax
+ divb %bl
+ cmpb $1, %al
+ jbe sipi_complete /* only LAPIC ID of a core */
+
+ /* For a hyper-threading processor, cache must not be disabled
+ * on an AP on the same physical package with the BSP.
+ */
+
+hyper_threading_cpu:
+
+ /* delay 10 ms */
+ movl $10000, %ecx
+1: inb $0x80, %al
+ dec %ecx
+ jnz 1b
+
+ post_code(0x25)
+
+ /* Send Start IPI to all excluding ourself. */
+ movl LAPIC(ICR), %edi
+ movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax
+1: movl %eax, (%edi)
+ movl $0x30, %ecx
+2: pause
+ dec %ecx
+ jnz 2b
+ movl (%edi), %ecx
+ andl $LAPIC_ICR_BUSY, %ecx
+ jnz 1b
+
+ /* delay 250 us */
+ movl $250, %ecx
+1: inb $0x80, %al
+ dec %ecx
+ jnz 1b
+
+ post_code(0x26)
+
+ /* Wait for sibling CPU to start. */
+1: movl $(MTRR_PHYS_BASE(0)), %ecx
+ rdmsr
+ andl %eax, %eax
+ jnz sipi_complete
+
+ movl $0x30, %ecx
+2: pause
+ dec %ecx
+ jnz 2b
+ jmp 1b
+
+
+ap_init:
+ post_code(0x27)
+
+ /* Do not disable cache (so BSP can enable it). */
+ movl %cr0, %eax
+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+ movl %eax, %cr0
+
+ post_code(0x28)
+
+ /* MTRR registers are shared between HT siblings. */
+ movl $(MTRR_PHYS_BASE(0)), %ecx
+ movl $(1 << 12), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ post_code(0x29)
+
+ap_halt:
+ cli
+1: hlt
+ jmp 1b
+
+
+
+sipi_complete:
+
+ post_code(0x2a)
+
+ /* Set Cache-as-RAM base address. */
+ movl $(MTRR_PHYS_BASE(0)), %ecx
+ movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ /* Set Cache-as-RAM mask. */
+ movl $(MTRR_PHYS_MASK(0)), %ecx
+ rdmsr
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+ wrmsr
+
+ post_code(0x2b)
+
+ /* Enable MTRR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ orl $MTRR_DEF_TYPE_EN, %eax
+ wrmsr
+
+ /* Enable L2 cache Write-Back (WBINVD and FLUSH#).
+ *
+ * MSR is set when DisplayFamily_DisplayModel is one of:
+ * 06_0x, 06_17, 06_1C
+ *
+ * Description says this bit enables use of WBINVD and FLUSH#.
+ * Should this be set only after the system bus and/or memory
+ * controller can successfully handle write cycles?
+ */
+
+#define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */
+#define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4))
+
+ movl $1, %eax
+ cpuid
+ movl %eax, %ebx
+ andl $EAX_FAMILY(0x0f), %eax
+ cmpl $EAX_FAMILY(0x06), %eax
+ jne no_msr_11e
+ movl %ebx, %eax
+ andl $EAX_MODEL(0xff), %eax
+ cmpl $EAX_MODEL(0x17), %eax
+ je has_msr_11e
+ cmpl $EAX_MODEL(0x1c), %eax
+ je has_msr_11e
+ andl $EAX_MODEL(0xf0), %eax
+ cmpl $EAX_MODEL(0x00), %eax
+ jne no_msr_11e
+has_msr_11e:
+ movl $0x11e, %ecx
+ rdmsr
+ orl $(1 << 8), %eax
+ wrmsr
+no_msr_11e:
+
+ post_code(0x2c)
+
+ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+ movl %cr0, %eax
+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+ invd
+ movl %eax, %cr0
+
+ /* Clear the cache memory region. This will also fill up the cache. */
+ cld
+ xorl %eax, %eax
+ movl $CACHE_AS_RAM_BASE, %edi
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
+ rep stosl
+
+ post_code(0x2d)
+ /* Enable Cache-as-RAM mode by disabling cache. */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ post_code(0x2e)
+ /* Enable cache. */
+ movl %cr0, %eax
+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+ movl %eax, %cr0
+
+ /* Setup the stack. */
+ mov $_car_stack_end, %esp
+
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the two pushes below. */
+ andl $0xfffffff0, %esp
+ sub $8, %esp
+
+ /*push TSC value to stack*/
+ movd %mm2, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm1, %eax
+ pushl %eax /* tsc[31:0] */
+
+before_romstage:
+ post_code(0x29)
+ call bootblock_c_entry
+
+ /* Should never see this postcode */
+ post_code(POST_DEAD_CODE)
+
+.Lhlt:
+ hlt
+ jmp .Lhlt
+
+fixed_mtrr_list:
+ .word MTRR_FIX_64K_00000
+ .word MTRR_FIX_16K_80000
+ .word MTRR_FIX_16K_A0000
+ .word MTRR_FIX_4K_C0000
+ .word MTRR_FIX_4K_C8000
+ .word MTRR_FIX_4K_D0000
+ .word MTRR_FIX_4K_D8000
+ .word MTRR_FIX_4K_E0000
+ .word MTRR_FIX_4K_E8000
+ .word MTRR_FIX_4K_F0000
+ .word MTRR_FIX_4K_F8000
+fixed_mtrr_list_size = . - fixed_mtrr_list
+
+_cache_as_ram_setup_end:
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8b227bd..9fec0d2 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -23,4 +23,11 @@
hex
default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+ help
+ The amount of anticipated stack usage inCAR by bootblock
+ and other stages.
+
endif # CPU_INTEL_SOCKET_LGA775
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index ceb084c..a37a1ca 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -13,7 +13,13 @@
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
+ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
+else
+bootblock-y += ../car/p4-netburst/cache_as_ram_bootblock.S
+bootblock-y += ../car/bootblock.c
+endif
+
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c
diff --git a/src/mainboard/intel/dg41wv/Makefile.inc b/src/mainboard/intel/dg41wv/Makefile.inc
index f3d7e76..abfc473 100644
--- a/src/mainboard/intel/dg41wv/Makefile.inc
+++ b/src/mainboard/intel/dg41wv/Makefile.inc
@@ -1,2 +1,3 @@
+bootblock-y += bootblock.c
ramstage-y += cstates.c
romstage-y += gpio.c
diff --git a/src/mainboard/intel/dg41wv/bootblock.c b/src/mainboard/intel/dg41wv/bootblock.c
new file mode 100644
index 0000000..7d1828f
--- /dev/null
+++ b/src/mainboard/intel/dg41wv/bootblock.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <arch/io.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
+#include <superio/winbond/common/winbond.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
+ /* Fixed IO decode ranges */
+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
+ /* LPC enable devices */
+ pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+
+ /* Set GPIOs on superio, enable UART */
+ pnp_enter_ext_func_mode(SERIAL_DEV);
+ pnp_set_logical_device(SERIAL_DEV);
+
+ pnp_write_config(SERIAL_DEV, 0x2c, 0x13);
+
+ pnp_exit_ext_func_mode(SERIAL_DEV);
+
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 610f785..549c140 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -31,6 +31,8 @@
select CACHE_MRC_SETTINGS
select POSTCAR_STAGE
select POSTCAR_CONSOLE
+ select C_ENVIRONMENT_BOOTBLOCK
+ select BOOTBLOCK_CONSOLE
config CBFS_SIZE
hex
diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc
index 3118b09..79dfa38 100644
--- a/src/northbridge/intel/x4x/Makefile.inc
+++ b/src/northbridge/intel/x4x/Makefile.inc
@@ -16,6 +16,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y)
+bootblock-y += bootblock_gcc.c
+
romstage-y += early_init.c
romstage-y += raminit.c
romstage-y += raminit_ddr23.c
diff --git a/src/northbridge/intel/x4x/bootblock_gcc.c b/src/northbridge/intel/x4x/bootblock_gcc.c
new file mode 100644
index 0000000..50a35ce
--- /dev/null
+++ b/src/northbridge/intel/x4x/bootblock_gcc.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/intel/car/bootblock.h>
+#include "iomap.h"
+#include "x4x.h"
+
+void bootblock_early_northbridge_init(void)
+{
+ uint32_t reg32;
+
+ /* Disable LaGrande Technology (LT) */
+ reg32 = TPM32(0);
+
+ reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
+ pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
+}
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index bb68d93..4a9db4e 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
+bootblock-y += bootblock_gcc.c
+
ramstage-y += i82801gx.c
ramstage-y += ac97.c
ramstage-y += azalia.c
diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c
new file mode 100644
index 0000000..77a7161
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/intel/car/bootblock.h>
+#include "i82801gx.h"
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(void)
+{
+ u8 reg8;
+ pci_devfn_t dev;
+
+ dev = PCI_DEV(0, 0x1f, 0);
+
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+
+static void map_rcba(void)
+{
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+
+ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+}
+
+static void enable_port80_on_lpc(void)
+{
+ /* Enable port 80 POST on LPC. The chipset does this by default,
+ * but it doesn't appear to hurt anything. */
+ u32 gcs = RCBA32(GCS);
+ gcs = gcs & ~0x4;
+ RCBA32(GCS) = gcs;
+}
+
+void bootblock_early_southbridge_init(void)
+{
+ map_rcba();
+ enable_spi_prefetch();
+ enable_port80_on_lpc();
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(RC) = (1 << 2);
+}
diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc
index b0b7b8c..a98c366 100644
--- a/src/superio/winbond/Makefile.inc
+++ b/src/superio/winbond/Makefile.inc
@@ -14,6 +14,7 @@
##
## include generic winbond pre-ram stage driver
+bootblock-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c
romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c
subdirs-y += w83627dhg
diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc
index 7d9dc97..4075a41 100644
--- a/src/superio/winbond/w83627dhg/Makefile.inc
+++ b/src/superio/winbond/w83627dhg/Makefile.inc
@@ -15,5 +15,6 @@
## GNU General Public License for more details.
##
+bootblock-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c
romstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c
ramstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.c
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8984d430a92182ecbabf7e97e054e5550d4fde66
Gerrit-Change-Number: 27032
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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