[coreboot-gerrit] Change in coreboot[master]: mediatek/mt8183: add pll and clock init support
Tristan Hsieh (Code Review)
gerrit at coreboot.org
Tue Jun 12 15:47:48 CEST 2018
Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27031
Change subject: mediatek/mt8183: add pll and clock init support
......................................................................
mediatek/mt8183: add pll and clock init support
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c
Signed-off-by: Weiyi Lu <weiyi.lu at mediatek.com>
---
M src/soc/mediatek/mt8183/Makefile.inc
A src/soc/mediatek/mt8183/bootblock.c
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/mcucfg.h
A src/soc/mediatek/mt8183/include/soc/pll.h
A src/soc/mediatek/mt8183/pll.c
6 files changed, 1,137 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27031/1
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index e827cd8..49c88ef 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -1,7 +1,9 @@
ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)
+bootblock-y += bootblock.c
bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
bootblock-y += ../common/mtcmos.c mtcmos_extend.c
+bootblock-y += pll.c
bootblock-$(CONFIG_SPI_FLASH) += spi.c
bootblock-y += ../common/timer.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
diff --git a/src/soc/mediatek/mt8183/bootblock.c b/src/soc/mediatek/mt8183/bootblock.c
new file mode 100644
index 0000000..e4c331e
--- /dev/null
+++ b/src/soc/mediatek/mt8183/bootblock.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/pll.h>
+
+void bootblock_soc_init(void)
+{
+ mt_pll_init();
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index 251e7f7..b616aac 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -17,14 +17,17 @@
#define __SOC_MEDIATEK_MT8183_INCLUDE_SOC_ADDRESSMAP_H__
enum {
+ MCUCFG_BASE = 0x0C530000,
IO_PHYS = 0x10000000,
DDR_BASE = 0x40000000
};
enum {
+ CKSYS_BASE = IO_PHYS,
INFRACFG_AO_BASE = IO_PHYS + 0x00001000,
SPM_BASE = IO_PHYS + 0x00006000,
GPT_BASE = IO_PHYS + 0x00008000,
+ APMIXED_BASE = IO_PHYS + 0x0000C000,
UART0_BASE = IO_PHYS + 0x01002000,
SMI_BASE = IO_PHYS + 0x04019000,
};
diff --git a/src/soc/mediatek/mt8183/include/soc/mcucfg.h b/src/soc/mediatek/mt8183/include/soc/mcucfg.h
new file mode 100644
index 0000000..0a1232a
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/mcucfg.h
@@ -0,0 +1,386 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_MCUCFG_H
+#define SOC_MEDIATEK_MT8183_MCUCFG_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8183_mcucfg_regs {
+ u32 mp0_ca7l_cache_config;
+ u32 mp0_cpu0_mem_delsel0;
+ u32 mp0_cpu0_mem_delsel1;
+ u32 reserved1[6];
+ u32 mp0_cache_mem_delsel0;
+ u32 mp0_cache_mem_delsel1;
+ u32 mp0_axi_config;
+ u32 mp0_misc_config0;
+ u32 reserved2[1];
+ u32 mp0_misc_config2;
+ u32 mp0_misc_config3;
+ u32 mp0_misc_config4;
+ u32 mp0_misc_config5;
+ u32 mp0_misc_config6;
+ u32 mp0_misc_config7;
+ u32 mp0_misc_config8;
+ u32 mp0_misc_config9;
+ u32 mp0_ca7l_cfg_dis;
+ u32 mp0_ca7l_clken_ctrl;
+ u32 mp0_ca7l_rst_ctrl;
+ u32 mp0_ca7l_misc_config;
+ u32 mp0_ca7l_dbg_pwr_ctrl;
+ u32 mp0_rw_rsvd0;
+ u32 mp0_rw_rsvd1;
+ u32 mp0_ro_rsvd;
+ u32 reserved3[1];
+ u32 mp0_l2_cache_parity1_rdata;
+ u32 mp0_l2_cache_parity2_rdata;
+ u32 reserved4[1];
+ u32 mp0_rgu_dcm_config;
+ u32 mp0_ca53_specific_ctrl;
+ u32 mp0_esr_case;
+ u32 mp0_esr_mask;
+ u32 mp0_esr_trig_en;
+ u32 reserved5[1];
+ u32 mp0_ses_cg_en;
+ u32 reserved6[216];
+ u32 mp_dbg_ctrl;
+ u32 reserved7[1];
+ u32 mp0_ca7l_ir_mon;
+ u32 reserved8[32];
+ u32 mp_dfd_ctrl;
+ u32 dfd_cnt_l;
+ u32 dfd_cnt_h;
+ u32 misccfg_ro_rsvd;
+ u32 reserved9[1];
+ u32 dvm_dbg_monitor_gpu;
+ u32 dvm_dbg_monitor_psys;
+ u32 dvm_dbg_monitor_mp1;
+ u32 dvm_dbg_monitor_mp0;
+ u32 dvm_dbg_monitor_mp2;
+ u32 reserved10[2];
+ u32 dvm_op_arid_mp0;
+ u32 dvm_op_arid_mp1;
+ u32 dvm_op_arid_mp2;
+ u32 reserved11[5];
+ u32 cci_s6_if_debug;
+ u32 reserved12[7];
+ u32 mp1_rst_status;
+ u32 mp1_dbg_ctrl;
+ u32 mp1_dbg_flag;
+ u32 mp1_ca7l_ir_mon;
+ u32 reserved13[32];
+ u32 mcusys_dbg_mon_sel_a;
+ u32 mcusys_dbg_mon;
+ u32 misccfg_sec_vio_status0;
+ u32 misccfg_sec_vio_status1;
+ u32 cci_top_if_debug;
+ u32 cci_m0_if_debug;
+ u32 cci_m1_if_debug;
+ u32 cci_m2_if_debug;
+ u32 cci_s1_if_debug;
+ u32 cci_s2_if_debug;
+ u32 cci_s3_if_debug;
+ u32 cci_s4_if_debug;
+ u32 cci_m0_tra_debug;
+ u32 cci_m1_tra_debug;
+ u32 cci_m2_tra_debug;
+ u32 cci_s1_tra_debug;
+ u32 cci_s2_tra_debug;
+ u32 cci_s3_tra_debug;
+ u32 cci_s4_tra_debug;
+ u32 cci_tra_dbg_cfg;
+ u32 cci_s5_if_debug;
+ u32 cci_s5_tra_debug;
+ u32 gic500_int_mask;
+ u32 core_rst_en_latch;
+ u32 reserved14[3];
+ u32 dbg_core_ret;
+ u32 mcusys_config_a;
+ u32 mcusys_config1_a;
+ u32 mcusys_gic_peribase_a;
+ u32 mcusys_pinmux;
+ u32 sec_range0_start;
+ u32 sec_range0_end;
+ u32 sec_range_enable;
+ u32 l2c_mm_base;
+ u32 reserved15[8];
+ u32 aclken_div;
+ u32 pclken_div;
+ u32 l2c_sram_ctrl;
+ u32 armpll_jit_ctrl;
+ u32 cci_addrmap;
+ u32 cci_config;
+ u32 cci_periphbase;
+ u32 cci_nevntcntovfl;
+ u32 cci_status;
+ u32 cci_acel_s1_ctrl;
+ u32 mcusys_bus_fabric_dcm_ctrl;
+ u32 mcu_misc_dcm_ctrl;
+ u32 xgpt_ctl;
+ u32 xgpt_idx;
+ u32 reserved16[3];
+ u32 mcusys_rw_rsvd0;
+ u32 mcusys_rw_rsvd1;
+ u32 reserved17[13];
+ u32 gic500_delsel_ctl;
+ u32 etb_delsel_ctl;
+ u32 etb_rst_ctl;
+ u32 reserved18[13];
+ u32 mp_gen_timer_reset_mask_secur_en;
+ u32 mp_gen_timer_reset_mask_0;
+ u32 mp_gen_timer_reset_mask_1;
+ u32 mp_gen_timer_reset_mask_2;
+ u32 mp_gen_timer_reset_mask_3;
+ u32 mp_gen_timer_reset_mask_4;
+ u32 mp_gen_timer_reset_mask_5;
+ u32 mp_gen_timer_reset_mask_6;
+ u32 mp_gen_timer_reset_mask_7;
+ u32 reserved19[7];
+ u32 mp_cci_adb400_dcm_config;
+ u32 mp_sync_dcm_config;
+ u32 reserved20[1];
+ u32 mp_sync_dcm_cluster_config;
+ u32 sw_udi;
+ u32 reserved21[1];
+ u32 gic_sync_dcm;
+ u32 big_dbg_pwr_ctrl;
+ u32 gic_cpu_periphbase;
+ u32 axi_cpu_config;
+ u32 reserved22[2];
+ u32 mcsib_sys_ctrl1;
+ u32 mcsib_sys_ctrl2;
+ u32 mcsib_sys_ctrl3;
+ u32 mcsib_sys_ctrl4;
+ u32 mcsib_dbg_ctrl1;
+ u32 pwrmcu_apb2to1;
+ u32 reserved23[1];
+ u32 mp1_spmc;
+ u32 reserved24[1];
+ u32 mp1_spmc_sram_ctl;
+ u32 reserved25[1];
+ u32 mp1_sw_rst_wait_cycle;
+ u32 mp0_pll_divider_cfg;
+ u32 reserved26[1];
+ u32 mp2_pll_divider_cfg;
+ u32 reserved27[5];
+ u32 bus_pll_divider_cfg;
+ u32 reserved28[7];
+ u32 clusterid_aff1;
+ u32 clusterid_aff2;
+ u32 hack_ice_rom_table_access;
+ u32 mp_top_mem_delay_cfg;
+ u32 l2c_cfg_mp0;
+ u32 reserved29[1];
+ u32 l2c_cfg_mp2;
+ u32 reserved30[1];
+ u32 cci_bw_pmu_ctl;
+ u32 cci_bw_pmu_cnt0to1_sel;
+ u32 cci_bw_pmu_cnt2to3_sel;
+ u32 cci_bw_pmu_cnt4to5_sel;
+ u32 cci_bw_pmu_cnt6to7_sel;
+ u32 cci_bw_pmu_cnt0to3_mask;
+ u32 cci_bw_pmu_cnt4to7_mask;
+ u32 cci_bw_pmu_ref_cnt;
+ u32 cci_bw_pmu_acc_cnt0;
+ u32 cci_bw_pmu_acc_cnt1;
+ u32 cci_bw_pmu_acc_cnt2;
+ u32 cci_bw_pmu_acc_cnt3;
+ u32 cci_bw_pmu_acc_cnt4;
+ u32 cci_bw_pmu_acc_cnt5;
+ u32 cci_bw_pmu_acc_cnt6;
+ u32 cci_bw_pmu_acc_cnt7;
+ u32 reserved31[8];
+ u32 cci_bw_pmu_id_ext_cnt0to3;
+ u32 cci_bw_pmu_id_ext_cnt4to7;
+ u32 cci_bw_pmu_mask_ext_cnt0to3;
+ u32 cci_bw_pmu_mask_ext_cnt4to7;
+ u32 reserved32[16];
+ u32 etb_acc_ctl;
+ u32 etb_ck_ctl;
+ u32 reserved33[4];
+ u32 mbista_mp1_ocp_con;
+ u32 reserved34[1];
+ u32 mbista_gic_con;
+ u32 mbista_gic_result;
+ u32 mbista_mcsib_sf1_con;
+ u32 mbista_mcsib_sf1_result;
+ u32 mbista_mcsib_sf2_con;
+ u32 mbista_mcsib_sf2_result;
+ u32 reserved35[2];
+ u32 mbista_rstb;
+ u32 mbista_all_result;
+ u32 reserved36[2];
+ u32 mp0_hang_monitor_ctrl0;
+ u32 mp0_hang_monitor_ctrl1;
+ u32 reserved37[2];
+ u32 mp1_hang_monitor_ctrl0;
+ u32 mp1_hang_monitor_ctrl1;
+ u32 reserved38[2];
+ u32 mp2_hang_monitor_ctrl0;
+ u32 mp2_hang_monitor_ctrl1;
+ u32 reserved39[6];
+ u32 gpu_hang_monitor_ctrl0;
+ u32 gpu_hang_monitor_ctrl1;
+ u32 reserved40[2];
+ u32 psys_hang_monitor_ctrl0;
+ u32 psys_hang_monitor_ctrl1;
+ u32 reserved41[42];
+ u32 sec_pol_ctl_en0;
+ u32 sec_pol_ctl_en1;
+ u32 sec_pol_ctl_en2;
+ u32 sec_pol_ctl_en3;
+ u32 sec_pol_ctl_en4;
+ u32 sec_pol_ctl_en5;
+ u32 sec_pol_ctl_en6;
+ u32 sec_pol_ctl_en7;
+ u32 sec_pol_ctl_en8;
+ u32 sec_pol_ctl_en9;
+ u32 sec_pol_ctl_en10;
+ u32 sec_pol_ctl_en11;
+ u32 sec_pol_ctl_en12;
+ u32 sec_pol_ctl_en13;
+ u32 sec_pol_ctl_en14;
+ u32 sec_pol_ctl_en15;
+ u32 sec_pol_ctl_en16;
+ u32 sec_pol_ctl_en17;
+ u32 sec_pol_ctl_en18;
+ u32 sec_pol_ctl_en19;
+ u32 reserved42[12];
+ u32 int_pol_ctl0;
+ u32 int_pol_ctl1;
+ u32 int_pol_ctl2;
+ u32 int_pol_ctl3;
+ u32 int_pol_ctl4;
+ u32 int_pol_ctl5;
+ u32 int_pol_ctl6;
+ u32 int_pol_ctl7;
+ u32 int_pol_ctl8;
+ u32 int_pol_ctl9;
+ u32 int_pol_ctl10;
+ u32 int_pol_ctl11;
+ u32 int_pol_ctl12;
+ u32 int_pol_ctl13;
+ u32 int_pol_ctl14;
+ u32 int_pol_ctl15;
+ u32 int_pol_ctl16;
+ u32 int_pol_ctl17;
+ u32 int_pol_ctl18;
+ u32 int_pol_ctl19;
+ u32 reserved43[12];
+ u32 dfd_internal_ctl;
+ u32 dfd_internal_counter;
+ u32 dfd_internal_pwr_on;
+ u32 dfd_internal_chain_legth_0;
+ u32 dfd_internal_shift_clk_ratio;
+ u32 dfd_internal_counter_return;
+ u32 dfd_internal_sram_access;
+ u32 dfd_internal_chain_length_1;
+ u32 dfd_internal_chain_length_2;
+ u32 dfd_internal_chain_length_3;
+ u32 dfd_internal_test_so_0;
+ u32 dfd_internal_test_so_1;
+ u32 dfd_internal_num_of_test_so_gp;
+ u32 dfd_internal_test_so_over_64;
+ u32 dfd_internal_mask_out;
+ u32 dfd_internal_sw_ns_trigger;
+ u32 dfd_internal_mcsib;
+ u32 dfd_internal_mcsib_sel_status;
+ u32 dfd_internal_sram_base_addr;
+ u32 dfd_internal_sram_delsel;
+ u32 mcsib_iccs_ctrl1;
+ u32 reserved44[1];
+ u32 mcu_all_pwr_on_ctrl;
+ u32 emi_wfifo;
+ u32 mcsia_dcm_en;
+ u32 reserved45[294];
+ u32 mcu_apb_base;
+ u32 reserved46[384];
+ u32 mp0_cpu_avg_stall_ratio;
+ u32 mp0_cpu0_avg_stall_ratio_ctrl;
+ u32 mp0_cpu1_avg_stall_ratio_ctrl;
+ u32 mp0_cpu2_avg_stall_ratio_ctrl;
+ u32 mp0_cpu3_avg_stall_ratio_ctrl;
+ u32 mp0_avg_stall_ratio_status;
+ u32 mp0_cpu0_stall_counter;
+ u32 mp0_cpu1_stall_counter;
+ u32 mp0_cpu2_stall_counter;
+ u32 mp0_cpu3_stall_counter;
+ u32 mp0_cpu0_non_wfi_counter;
+ u32 mp0_cpu1_non_wfi_counter;
+ u32 mp0_cpu2_non_wfi_counter;
+ u32 mp0_cpu3_non_wfi_counter;
+ u32 reserved47[370];
+ u32 cpusys0_sparkvretcntrl;
+ u32 cpusys0_sparken;
+ u32 cpusys0_amuxsel;
+ u32 cpusys0_cg_dis;
+ u32 cpusys0_cpu0_counter;
+ u32 cpusys0_cpu1_counter;
+ u32 cpusys0_cpu2_counter;
+ u32 cpusys0_cpu3_counter;
+ u32 cpusys0_spark_debug_overwrite;
+ u32 reserved48[3];
+ u32 cpusys0_cpu0_spmc_ctl;
+ u32 cpusys0_cpu1_spmc_ctl;
+ u32 cpusys0_cpu2_spmc_ctl;
+ u32 cpusys0_cpu3_spmc_ctl;
+ u32 sesv3_rg_toggle;
+ u32 reserved49[7];
+ u32 mp0_sync_dcm_cgavg_ctrl;
+ u32 mp0_sync_dcm_cgavg_fact;
+ u32 mp0_sync_dcm_cgavg_rfact;
+ u32 mp0_sync_dcm_cgavg;
+};
+
+check_member(mt8183_mcucfg_regs, mp0_cache_mem_delsel0, 0x0024);
+check_member(mt8183_mcucfg_regs, mp_dbg_ctrl, 0x0404);
+check_member(mt8183_mcucfg_regs, mp_dfd_ctrl, 0x0490);
+check_member(mt8183_mcucfg_regs, dvm_op_arid_mp0, 0x04c0);
+check_member(mt8183_mcucfg_regs, cci_s6_if_debug, 0x04e0);
+check_member(mt8183_mcucfg_regs, mp1_rst_status, 0x0500);
+check_member(mt8183_mcucfg_regs, mcusys_dbg_mon_sel_a, 0x0590);
+check_member(mt8183_mcucfg_regs, dbg_core_ret, 0x05fc);
+check_member(mt8183_mcucfg_regs, aclken_div, 0x0640);
+check_member(mt8183_mcucfg_regs, mcusys_rw_rsvd0, 0x0684);
+check_member(mt8183_mcucfg_regs, gic500_delsel_ctl, 0x06c0);
+check_member(mt8183_mcucfg_regs, mp_gen_timer_reset_mask_secur_en, 0x0700);
+check_member(mt8183_mcucfg_regs, mp_cci_adb400_dcm_config, 0x0740);
+check_member(mt8183_mcucfg_regs, mcsib_sys_ctrl1, 0x0770);
+check_member(mt8183_mcucfg_regs, bus_pll_divider_cfg, 0x07c0);
+check_member(mt8183_mcucfg_regs, clusterid_aff1, 0x07e0);
+check_member(mt8183_mcucfg_regs, cci_bw_pmu_id_ext_cnt0to3, 0x0860);
+check_member(mt8183_mcucfg_regs, etb_acc_ctl, 0x08b0);
+check_member(mt8183_mcucfg_regs, mbista_mp1_ocp_con, 0x08c8);
+check_member(mt8183_mcucfg_regs, mbista_rstb, 0x08f0);
+check_member(mt8183_mcucfg_regs, mp0_hang_monitor_ctrl0, 0x0900);
+check_member(mt8183_mcucfg_regs, mp1_hang_monitor_ctrl0, 0x0910);
+check_member(mt8183_mcucfg_regs, mp2_hang_monitor_ctrl0, 0x0920);
+check_member(mt8183_mcucfg_regs, gpu_hang_monitor_ctrl0, 0x0940);
+check_member(mt8183_mcucfg_regs, psys_hang_monitor_ctrl0, 0x0950);
+check_member(mt8183_mcucfg_regs, sec_pol_ctl_en0, 0x0a00);
+check_member(mt8183_mcucfg_regs, int_pol_ctl0, 0x0a80);
+check_member(mt8183_mcucfg_regs, dfd_internal_ctl, 0x0b00);
+check_member(mt8183_mcucfg_regs, mcu_apb_base, 0x0ffc);
+check_member(mt8183_mcucfg_regs, mp0_cpu_avg_stall_ratio, 0x1600);
+check_member(mt8183_mcucfg_regs, cpusys0_sparkvretcntrl, 0x1c00);
+check_member(mt8183_mcucfg_regs, cpusys0_cpu0_spmc_ctl, 0x1c30);
+check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg_ctrl, 0x1c60);
+check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg, 0x1c6c);
+
+static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;
+
+#endif /* SOC_MEDIATEK_MT8183_MCUCFG_H */
diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h
new file mode 100644
index 0000000..42dd9d9
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/pll.h
@@ -0,0 +1,251 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_PLL_H
+#define SOC_MEDIATEK_MT8183_PLL_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8183_topckgen_regs {
+ u32 clk_mode;
+ u32 clk_cfg_update;
+ u32 clk_cfg_update1;
+ u32 reserved1[13];
+ u32 clk_cfg_0;
+ u32 clk_cfg_0_set;
+ u32 clk_cfg_0_clr;
+ u32 reserved2[1];
+ u32 clk_cfg_1;
+ u32 clk_cfg_1_set;
+ u32 clk_cfg_1_clr;
+ u32 reserved3[1];
+ u32 clk_cfg_2;
+ u32 clk_cfg_2_set;
+ u32 clk_cfg_2_clr;
+ u32 reserved4[1];
+ u32 clk_cfg_3;
+ u32 clk_cfg_3_set;
+ u32 clk_cfg_3_clr;
+ u32 reserved5[1];
+ u32 clk_cfg_4;
+ u32 clk_cfg_4_set;
+ u32 clk_cfg_4_clr;
+ u32 reserved6[1];
+ u32 clk_cfg_5;
+ u32 clk_cfg_5_set;
+ u32 clk_cfg_5_clr;
+ u32 reserved7[1];
+ u32 clk_cfg_6;
+ u32 clk_cfg_6_set;
+ u32 clk_cfg_6_clr;
+ u32 reserved8[1];
+ u32 clk_cfg_7;
+ u32 clk_cfg_7_set;
+ u32 clk_cfg_7_clr;
+ u32 reserved9[1];
+ u32 clk_cfg_8;
+ u32 clk_cfg_8_set;
+ u32 clk_cfg_8_clr;
+ u32 reserved10[1];
+ u32 clk_cfg_9;
+ u32 clk_cfg_9_set;
+ u32 clk_cfg_9_clr;
+ u32 reserved11[1];
+ u32 clk_cfg_10;
+ u32 clk_cfg_10_set;
+ u32 clk_cfg_10_clr;
+ u32 reserved12[6];
+ u32 clk_misc_cfg_0;
+ u32 clk_misc_cfg_1;
+ u32 clk_dbg_cfg;
+ u32 reserved13[60];
+ u32 clk_scp_cfg_0;
+ u32 clk_scp_cfg_1;
+ u32 reserved14[6];
+ u32 clk26cali_0;
+ u32 clk26cali_1;
+ u32 reserved15[2];
+ u32 cksta_reg;
+ u32 cksta_reg1;
+ u32 reserved16[50];
+ u32 clkmon_clk_sel_reg;
+ u32 clkmon_k1_reg;
+ u32 reserved17[6];
+ u32 clk_auddiv_0;
+ u32 clk_auddiv_1;
+ u32 clk_auddiv_2;
+ u32 aud_top_cfg;
+ u32 aud_top_mon;
+ u32 clk_auddiv_3;
+ u32 reserved18[50];
+ u32 clk_pdn_reg;
+ u32 reserved19[63];
+ u32 clk_extck_reg;
+ u32 reserved20[79];
+ u32 clk_cfg_20;
+ u32 clk_cfg_20_set;
+ u32 clk_cfg_20_clr;
+};
+
+check_member(mt8183_topckgen_regs, clk_cfg_0, 0x0040);
+check_member(mt8183_topckgen_regs, clk_misc_cfg_0, 0x0104);
+check_member(mt8183_topckgen_regs, clk_scp_cfg_0, 0x0200);
+check_member(mt8183_topckgen_regs, clk26cali_0, 0x0220);
+check_member(mt8183_topckgen_regs, cksta_reg, 0x0230);
+check_member(mt8183_topckgen_regs, clkmon_clk_sel_reg, 0x0300);
+check_member(mt8183_topckgen_regs, clk_auddiv_0, 0x0320);
+check_member(mt8183_topckgen_regs, clk_pdn_reg, 0x0400);
+check_member(mt8183_topckgen_regs, clk_extck_reg, 0x0500);
+check_member(mt8183_topckgen_regs, clk_cfg_20, 0x0640);
+check_member(mt8183_topckgen_regs, clk_cfg_20_clr, 0x0648);
+
+struct mt8183_apmixed_regs {
+ u32 ap_pll_con0;
+ u32 ap_pll_con1;
+ u32 ap_pll_con2;
+ u32 ap_pll_con3;
+ u32 ap_pll_con4;
+ u32 ap_pll_con5;
+ u32 ap_pll_con6;
+ u32 ap_pll_con7;
+ u32 ap_pll_con8;
+ u32 clksq_stb_con0;
+ u32 pll_pwr_con0;
+ u32 pll_pwr_con1;
+ u32 pll_iso_con0;
+ u32 pll_iso_con1;
+ u32 pll_stb_con0;
+ u32 div_stb_con0;
+ u32 pll_chg_con0;
+ u32 pll_test_con0;
+ u32 pll_test_con1;
+ u32 reserved1[109];
+ u32 armpll_ll_con0;
+ u32 armpll_ll_con1;
+ u32 armpll_ll_con2;
+ u32 armpll_ll_pwr_con0;
+ u32 armpll_l_con0;
+ u32 armpll_l_con1;
+ u32 armpll_l_con2;
+ u32 armpll_l_pwr_con0;
+ u32 mainpll_con0;
+ u32 mainpll_con1;
+ u32 mainpll_con2;
+ u32 mainpll_pwr_con0;
+ u32 univpll_con0;
+ u32 univpll_con1;
+ u32 univpll_con2;
+ u32 univpll_pwr_con0;
+ u32 mfgpll_con0;
+ u32 mfgpll_con1;
+ u32 mfgpll_con2;
+ u32 mfgpll_pwr_con0;
+ u32 msdcpll_con0;
+ u32 msdcpll_con1;
+ u32 msdcpll_con2;
+ u32 msdcpll_pwr_con0;
+ u32 tvdpll_con0;
+ u32 tvdpll_con1;
+ u32 tvdpll_con2;
+ u32 tvdpll_pwr_con0;
+ u32 mmpll_con0;
+ u32 mmpll_con1;
+ u32 mmpll_con2;
+ u32 mmpll_pwr_con0;
+ u32 mpll_con0;
+ u32 mpll_con1;
+ u32 mpll_con2;
+ u32 mpll_pwr_con0;
+ u32 ccipll_con0;
+ u32 ccipll_con1;
+ u32 ccipll_con2;
+ u32 ccipll_pwr_con0;
+ u32 apll1_con0;
+ u32 apll1_con1;
+ u32 apll1_con2;
+ u32 apll1_con3;
+ u32 apll1_pwr_con0;
+ u32 apll2_con0;
+ u32 apll2_con1;
+ u32 apll2_con2;
+ u32 apll2_con3;
+ u32 apll2_pwr_con0;
+ u32 reserved2[78];
+ u32 ap_auxadc_con0;
+ u32 ap_auxadc_con1;
+ u32 ap_auxadc_con2;
+ u32 ap_auxadc_con3;
+ u32 ap_auxadc_con4;
+ u32 ap_auxadc_con5;
+ u32 reserved3[122];
+ u32 ts_con0;
+ u32 ts_con1;
+ u32 ts_con2;
+ u32 reserved4[61];
+ u32 ulposc_con0;
+ u32 ulposc_con1;
+ u32 ulposc2_con0;
+ u32 ulposc2_con1;
+ u32 reserved5[60];
+ u32 ap_abist_mon_con0;
+ u32 ap_abist_mon_con1;
+ u32 ap_abist_mon_con2;
+ u32 ap_abist_mon_con3;
+ u32 occscan_con0;
+ u32 clkdiv_con0;
+ u32 occscan_con1;
+ u32 occscan_con2;
+ u32 mcu_occscan_con0;
+ u32 reserved6[55];
+ u32 rsv_rw0_con0;
+ u32 rsv_rw1_con0;
+ u32 rsv_ro_con0;
+};
+
+check_member(mt8183_apmixed_regs, armpll_ll_con0, 0x0200);
+check_member(mt8183_apmixed_regs, ap_auxadc_con0, 0x0400);
+check_member(mt8183_apmixed_regs, ts_con0, 0x0600);
+check_member(mt8183_apmixed_regs, ulposc_con0, 0x0700);
+check_member(mt8183_apmixed_regs, ap_abist_mon_con0, 0x0800);
+check_member(mt8183_apmixed_regs, rsv_rw0_con0, 0x0900);
+check_member(mt8183_apmixed_regs, rsv_ro_con0, 0x0908);
+
+static struct mt8183_topckgen_regs *const mt8183_topckgen = (void *)CKSYS_BASE;
+static struct mt8183_apmixed_regs *const mt8183_apmixed = (void *)APMIXED_BASE;
+
+/* PLL rate */
+enum {
+ ARMPLL_LL_HZ = 1100 * MHz,
+ ARMPLL_L_HZ = 1200 * MHz,
+ CCIPLL_HZ = 598 * 2 * MHz,
+ MAINPLL_HZ = 1092 * MHz,
+ UNIVPLL_HZ = 1248UL * 2 * MHz,
+ MSDCPLL_HZ = 384 * MHz,
+ MMPLL_HZ = 3150UL * MHz,
+ MFGPLL_HZ = 512 * MHz,
+ TVDPLL_HZ = 594 * MHz,
+ APLL1_HZ = 180633600,
+ APLL2_HZ = 196608 * KHz,
+};
+
+/* top_div rate */
+enum {
+ CLK26M_HZ = 26 * MHz,
+};
+
+void mt_pll_init(void);
+
+#endif /* SOC_MEDIATEK_MT8183_PLL_H */
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
new file mode 100644
index 0000000..00a2fa8
--- /dev/null
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -0,0 +1,473 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <console/console.h>
+#include <delay.h>
+#include <stddef.h>
+
+#include <soc/addressmap.h>
+#include <soc/infracfg.h>
+#include <soc/mcucfg.h>
+#include <soc/mtcmos.h>
+#include <soc/mtcmos_extend.h>
+#include <soc/pll.h>
+
+#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))
+
+enum mux_id {
+ TOP_AXI_SEL,
+ TOP_MM_SEL,
+ TOP_IMG_SEL,
+ TOP_CAM_SEL,
+ TOP_DSP_SEL,
+ TOP_DSP1_SEL,
+ TOP_DSP2_SEL,
+ TOP_IPU_IF_SEL,
+ TOP_MFG_SEL,
+ TOP_MFG_52M_SEL,
+ TOP_CAMTG_SEL,
+ TOP_CAMTG2_SEL,
+ TOP_CAMTG3_SEL,
+ TOP_CAMTG4_SEL,
+ TOP_UART_SEL,
+ TOP_SPI_SEL,
+ TOP_MSDC50_0_HCLK_SEL,
+ TOP_MSDC50_0_SEL,
+ TOP_MSDC30_1_SEL,
+ TOP_MSDC30_2_SEL,
+ TOP_AUDIO_SEL,
+ TOP_AUD_INTBUS_SEL,
+ TOP_PMICSPI_SEL,
+ TOP_PWRAP_ULPOSC_SEL,
+ TOP_ATB_SEL,
+ TOP_PWRMCU_SEL,
+ TOP_DPI0_SEL,
+ TOP_SCAM_SEL,
+ TOP_DISP_PWM_SEL,
+ TOP_USB_TOP_SEL,
+ TOP_SSUSB_XHCI_SEL,
+ TOP_SPM_SEL,
+ TOP_I2C_SEL,
+ TOP_SCP_SEL,
+ TOP_SENINF_SEL,
+ TOP_DXCC_SEL,
+ TOP_AUD_ENGEN1_SEL,
+ TOP_AUD_ENGEN2_SEL,
+ TOP_AES_UFSFDE_SEL,
+ TOP_UFS_SEL,
+ TOP_AUD_1_SEL,
+ TOP_AUD_2_SEL,
+ TOP_NR_MUX
+};
+
+#define TOPCKGEN_REG(x) (CKSYS_BASE + offsetof(struct mt8183_topckgen_regs, x))
+#define APMIXED_REG(x) (APMIXED_BASE + offsetof(struct mt8183_apmixed_regs, x))
+
+struct mux {
+ void *reg;
+ u8 mux_shift;
+ u8 mux_width;
+ void *upd_reg;
+ u8 upd_shift;
+};
+
+#define MUX(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift) \
+ [_id] = { \
+ .reg = (void *)TOPCKGEN_REG(_reg), \
+ .mux_shift = _mux_shift, \
+ .mux_width = _mux_width, \
+ .upd_reg = (void *)TOPCKGEN_REG(_upd_reg), \
+ .upd_shift = _upd_shift, \
+ }
+
+static const struct mux muxes[] = {
+ /* CLK_CFG_0 */
+ MUX(TOP_AXI_SEL, clk_cfg_0, 0, 2, clk_cfg_update, 0),
+ MUX(TOP_MM_SEL, clk_cfg_0, 8, 3, clk_cfg_update, 1),
+ MUX(TOP_IMG_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2),
+ MUX(TOP_CAM_SEL, clk_cfg_0, 24, 4, clk_cfg_update, 3),
+ /* CLK_CFG_1 */
+ MUX(TOP_DSP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4),
+ MUX(TOP_DSP1_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5),
+ MUX(TOP_DSP2_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6),
+ MUX(TOP_IPU_IF_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7),
+ /* CLK_CFG_2 */
+ MUX(TOP_MFG_SEL, clk_cfg_2, 0, 2, clk_cfg_update, 8),
+ MUX(TOP_MFG_52M_SEL, clk_cfg_2, 8, 2, clk_cfg_update, 9),
+ MUX(TOP_CAMTG_SEL, clk_cfg_2, 16, 3, clk_cfg_update, 10),
+ MUX(TOP_CAMTG2_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11),
+ /* CLK_CFG_3 */
+ MUX(TOP_CAMTG3_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12),
+ MUX(TOP_CAMTG4_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13),
+ MUX(TOP_UART_SEL, clk_cfg_3, 16, 1, clk_cfg_update, 14),
+ MUX(TOP_SPI_SEL, clk_cfg_3, 24, 2, clk_cfg_update, 15),
+ /* CLK_CFG_4 */
+ MUX(TOP_MSDC50_0_HCLK_SEL, clk_cfg_4, 0, 2, clk_cfg_update, 16),
+ MUX(TOP_MSDC50_0_SEL, clk_cfg_4, 8, 3, clk_cfg_update, 17),
+ MUX(TOP_MSDC30_1_SEL, clk_cfg_4, 16, 3, clk_cfg_update, 18),
+ MUX(TOP_MSDC30_2_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19),
+ /* CLK_CFG_5 */
+ MUX(TOP_AUDIO_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20),
+ MUX(TOP_AUD_INTBUS_SEL, clk_cfg_5, 8, 2, clk_cfg_update, 21),
+ MUX(TOP_PMICSPI_SEL, clk_cfg_5, 16, 2, clk_cfg_update, 22),
+ MUX(TOP_PWRAP_ULPOSC_SEL, clk_cfg_5, 24, 2, clk_cfg_update, 23),
+ /* CLK_CFG_6 */
+ MUX(TOP_ATB_SEL, clk_cfg_6, 0, 2, clk_cfg_update, 24),
+ MUX(TOP_PWRMCU_SEL, clk_cfg_6, 8, 3, clk_cfg_update, 25),
+ MUX(TOP_DPI0_SEL, clk_cfg_6, 16, 4, clk_cfg_update, 26),
+ MUX(TOP_SCAM_SEL, clk_cfg_6, 24, 1, clk_cfg_update, 27),
+ /* CLK_CFG_7 */
+ MUX(TOP_DISP_PWM_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28),
+ MUX(TOP_USB_TOP_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29),
+ MUX(TOP_SSUSB_XHCI_SEL, clk_cfg_7, 16, 2, clk_cfg_update, 30),
+ MUX(TOP_SPM_SEL, clk_cfg_7, 24, 1, clk_cfg_update1, 0),
+ /* CLK_CFG_8 */
+ MUX(TOP_I2C_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1),
+ MUX(TOP_SCP_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2),
+ MUX(TOP_SENINF_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 3),
+ MUX(TOP_DXCC_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 4),
+ /* CLK_CFG_9 */
+ MUX(TOP_AUD_ENGEN1_SEL, clk_cfg_9, 0, 2, clk_cfg_update1, 5),
+ MUX(TOP_AUD_ENGEN2_SEL, clk_cfg_9, 8, 2, clk_cfg_update1, 6),
+ MUX(TOP_AES_UFSFDE_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 7),
+ MUX(TOP_UFS_SEL, clk_cfg_9, 24, 2, clk_cfg_update1, 8),
+ /* CLK_CFG_10 */
+ MUX(TOP_AUD_1_SEL, clk_cfg_10, 0, 1, clk_cfg_update1, 9),
+ MUX(TOP_AUD_2_SEL, clk_cfg_10, 8, 1, clk_cfg_update1, 10),
+};
+
+static void mux_set_sel(const struct mux *mux, u32 sel)
+{
+ u32 mask = GENMASK(mux->mux_width - 1, 0);
+ u32 val = read32(mux->reg);
+
+ val &= ~(mask << mux->mux_shift);
+ val |= (sel & mask) << mux->mux_shift;
+ write32(mux->reg, val);
+ write32(mux->upd_reg, 1 << mux->upd_shift);
+}
+
+#define PLL_PWR_ON (1 << 0)
+#define PLL_EN (1 << 0)
+#define PLL_ISO (1 << 1)
+#define PLL_RSTB (1 << 24)
+#define MMPLL_RSTB (1 << 23)
+#define PLL_PCW_CHG (1 << 31)
+#define PLL_POSTDIV_MASK 0x7
+#define PCW_INTEGER_BITS 8
+
+enum pll_id {
+ APMIXED_ARMPLL_LL,
+ APMIXED_ARMPLL_L,
+ APMIXED_CCIPLL,
+ APMIXED_MAINPLL,
+ APMIXED_UNIVPLL,
+ APMIXED_MSDCPLL,
+ APMIXED_MMPLL,
+ APMIXED_MFGPLL,
+ APMIXED_TVDPLL,
+ APMIXED_APLL1,
+ APMIXED_APLL2,
+ APMIXED_NR_PLL
+};
+
+const u32 pll_div_rate[] = {
+ 3800UL * MHz,
+ 1248 * MHz,
+ 624 * MHz,
+ 384 * MHz,
+ 200 * MHz,
+ 0,
+};
+
+struct pll {
+ void *reg;
+ void *pwr_reg;
+ u32 rstb;
+ u8 pcwbits;
+ void *div_reg;
+ u8 div_shift;
+ void *pcw_reg;
+ u8 pcw_shift;
+ const u32 *div_rate;
+};
+
+#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \
+ _pcw_reg, _pcw_shift, _div_rate) \
+ [_id] = { \
+ .reg = (void *)APMIXED_REG(_reg), \
+ .pwr_reg = (void *)APMIXED_REG(_pwr_reg), \
+ .rstb = _rstb, \
+ .pcwbits = _pcwbits, \
+ .div_reg = (void *)APMIXED_REG(_div_reg), \
+ .div_shift = _div_shift, \
+ .pcw_reg = (void *)APMIXED_REG(_pcw_reg), \
+ .pcw_shift = _pcw_shift, \
+ .div_rate = _div_rate, \
+ }
+
+static const struct pll plls[] = {
+ PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_pwr_con0, PLL_RSTB, 22,
+ armpll_ll_con1, 24, armpll_ll_con1, 0, pll_div_rate),
+ PLL(APMIXED_ARMPLL_L, armpll_l_con0, armpll_l_pwr_con0, PLL_RSTB, 22,
+ armpll_l_con1, 24, armpll_l_con1, 0, pll_div_rate),
+ PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_pwr_con0, PLL_RSTB, 22,
+ ccipll_con1, 24, ccipll_con1, 0, pll_div_rate),
+ PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0, PLL_RSTB, 22,
+ mainpll_con1, 24, mainpll_con1, 0, pll_div_rate),
+ PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0, PLL_RSTB, 22,
+ univpll_con1, 24, univpll_con1, 0, pll_div_rate),
+ PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0, 0, 22,
+ msdcpll_con1, 24, msdcpll_con1, 0, pll_div_rate),
+ PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0, MMPLL_RSTB, 22,
+ mmpll_con1, 24, mmpll_con1, 0, pll_div_rate),
+ PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_pwr_con0, 0, 22,
+ mfgpll_con1, 24, mfgpll_con1, 0, pll_div_rate),
+ PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0, 0, 22,
+ tvdpll_con1, 24, tvdpll_con1, 0, pll_div_rate),
+ PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0, 0, 32,
+ apll1_con0, 1, apll1_con1, 0, pll_div_rate),
+ PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0, 0, 32,
+ apll2_con0, 1, apll2_con1, 0, pll_div_rate),
+};
+
+static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv)
+{
+ u32 val;
+
+ /* set postdiv */
+ val = read32(pll->div_reg);
+ val &= ~(PLL_POSTDIV_MASK << pll->div_shift);
+ val |= postdiv << pll->div_shift;
+
+ /* postdiv and pcw need to set at the same time if on same register */
+ if (pll->div_reg != pll->pcw_reg) {
+ write32(pll->div_reg, val);
+ val = read32(pll->pcw_reg);
+ }
+
+ /* set pcw */
+ val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
+ val |= pcw << pll->pcw_shift;
+ if (pll->div_reg == pll->pcw_reg) {
+ val |= PLL_PCW_CHG;
+ write32(pll->pcw_reg, val);
+ } else {
+ write32(pll->pcw_reg, val);
+ val = read32(pll->div_reg);
+ val |= PLL_PCW_CHG;
+ write32(pll->div_reg, val);
+ }
+}
+
+static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv,
+ u32 freq)
+{
+ const u32 fin_hz = CLK26M_HZ;
+ const u32 *div_rate = pll->div_rate;
+ u32 val;
+
+ assert(freq <= div_rate[0]);
+ assert(freq >= 1 * GHz / 16);
+
+ for (val = 1; div_rate[val] != 0; val++) {
+ if (freq > div_rate[val])
+ break;
+ }
+ val--;
+ *postdiv = val;
+
+ /* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */
+ val += pll->pcwbits - PCW_INTEGER_BITS;
+
+ *pcw = ((u64)freq << val) / fin_hz;
+}
+
+static int pll_set_rate(const struct pll *pll, u32 rate)
+{
+ u32 pcw = 0;
+ u32 postdiv;
+
+ pll_calc_values(pll, &pcw, &postdiv, rate);
+ pll_set_rate_regs(pll, pcw, postdiv);
+
+ return 0;
+}
+
+void mt_pll_init(void)
+{
+ int i;
+
+ /* enable univpll & mainpll div */
+ setbits_le32(&mt8183_apmixed->ap_pll_con2, 0x1FFE << 16);
+
+ /* enable clock square1 low-pass filter */
+ setbits_le32(&mt8183_apmixed->ap_pll_con0, 0x2);
+
+ /*************
+ * xPLL PWR ON
+ **************/
+ for (i = 0; i < APMIXED_NR_PLL; i++)
+ setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
+
+ udelay(100);
+
+ /******************
+ * xPLL ISO Disable
+ *******************/
+ for (i = 0; i < APMIXED_NR_PLL; i++)
+ clrbits_le32(plls[i].pwr_reg, PLL_ISO);
+
+ udelay(50);
+
+ /********************
+ * xPLL Frequency Set
+ *********************/
+
+ pll_set_rate(&plls[APMIXED_ARMPLL_LL], ARMPLL_LL_HZ);
+ pll_set_rate(&plls[APMIXED_ARMPLL_L], ARMPLL_L_HZ);
+ pll_set_rate(&plls[APMIXED_CCIPLL], CCIPLL_HZ);
+ pll_set_rate(&plls[APMIXED_MAINPLL], MAINPLL_HZ);
+ pll_set_rate(&plls[APMIXED_UNIVPLL], UNIVPLL_HZ);
+ pll_set_rate(&plls[APMIXED_MSDCPLL], MSDCPLL_HZ);
+ pll_set_rate(&plls[APMIXED_MMPLL], MMPLL_HZ);
+ pll_set_rate(&plls[APMIXED_MFGPLL], MFGPLL_HZ);
+ pll_set_rate(&plls[APMIXED_TVDPLL], TVDPLL_HZ);
+ pll_set_rate(&plls[APMIXED_APLL1], APLL1_HZ);
+ pll_set_rate(&plls[APMIXED_APLL2], APLL2_HZ);
+
+ /********************
+ * AUDPLL Tuner Frequency Set
+ *********************/
+ write32(&mt8183_apmixed->apll1_con2,
+ read32(&mt8183_apmixed->apll1_con1) + 1);
+ write32(&mt8183_apmixed->apll2_con2,
+ read32(&mt8183_apmixed->apll2_con1) + 1);
+
+ /***********************
+ * xPLL Frequency Enable
+ ************************/
+ for (i = 0; i < APMIXED_NR_PLL; i++)
+ setbits_le32(plls[i].reg, PLL_EN);
+
+ udelay(50); /* wait for PLL stable */
+
+ /***************
+ * xPLL DIV RSTB
+ ****************/
+ for (i = 0; i < APMIXED_NR_PLL; i++) {
+ if (plls[i].rstb)
+ setbits_le32(plls[i].reg, plls[i].rstb);
+ }
+
+ /**************
+ * MCUCFG CLKMUX
+ ***************/
+
+ clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, 0x1f << 17,
+ 0x8 << 17);
+ clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, 0x1f << 17,
+ 0x8 << 17);
+ clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, 0x1f << 17,
+ 0x8 << 17);
+
+ clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, 0x3 << 9, 1 << 9);
+ clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, 0x3 << 9, 1 << 9);
+ clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, 0x3 << 9, 1 << 9);
+
+ /* enable infrasys DCM */
+ setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
+
+ /************
+ * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
+ *************/
+
+ /* CLK_CFG_0 */
+ mux_set_sel(&muxes[TOP_AXI_SEL], 2); /* 2: mainpll_d7 */
+ mux_set_sel(&muxes[TOP_MM_SEL], 1); /* 1: mmpll_d7 */
+ mux_set_sel(&muxes[TOP_IMG_SEL], 1); /* 1: mmpll_d6 */
+ mux_set_sel(&muxes[TOP_CAM_SEL], 1); /* 1: mainpll_d2 */
+ /* CLK_CFG_1 */
+ mux_set_sel(&muxes[TOP_DSP_SEL], 1); /* 1: mmpll_d6 */
+ mux_set_sel(&muxes[TOP_DSP1_SEL], 1); /* 1: mmpll_d6 */
+ mux_set_sel(&muxes[TOP_DSP2_SEL], 1); /* 1: mmpll_d6 */
+ mux_set_sel(&muxes[TOP_IPU_IF_SEL], 1); /* 1: mmpll_d6 */
+ /* CLK_CFG_2 */
+ mux_set_sel(&muxes[TOP_MFG_SEL], 1); /* 1: mfgpll_ck */
+ mux_set_sel(&muxes[TOP_MFG_52M_SEL], 3); /* 3: univpll_d3_d8 */
+ mux_set_sel(&muxes[TOP_CAMTG_SEL], 1); /* 1: univ_192m_d8 */
+ mux_set_sel(&muxes[TOP_CAMTG2_SEL], 1); /* 1: univ_192m_d8 */
+ /* CLK_CFG_3 */
+ mux_set_sel(&muxes[TOP_CAMTG3_SEL], 1); /* 1: univ_192m_d8 */
+ mux_set_sel(&muxes[TOP_CAMTG4_SEL], 1); /* 1: univ_192m_d8 */
+ mux_set_sel(&muxes[TOP_UART_SEL], 0); /* 0: clk26m */
+ mux_set_sel(&muxes[TOP_SPI_SEL], 1); /* 1: mainpll_d5_d2 */
+ /* CLK_CFG_4 */
+ mux_set_sel(&muxes[TOP_MSDC50_0_HCLK_SEL], 1); /* 1: mainpll_d2_d2 */
+ mux_set_sel(&muxes[TOP_MSDC50_0_SEL], 1); /* 1: msdcpll_ck */
+ mux_set_sel(&muxes[TOP_MSDC30_1_SEL], 4); /* 4: msdcpll_d2 */
+ mux_set_sel(&muxes[TOP_MSDC30_2_SEL], 1); /* 1: univpll_d3_d2 */
+ /* CLK_CFG_5 */
+ mux_set_sel(&muxes[TOP_AUDIO_SEL], 0); /* 0: clk26m */
+ mux_set_sel(&muxes[TOP_AUD_INTBUS_SEL], 1); /* 1: mainpll_d2_d4 */
+ mux_set_sel(&muxes[TOP_PMICSPI_SEL], 0); /* 0: clk26m */
+ mux_set_sel(&muxes[TOP_PWRAP_ULPOSC_SEL], 0); /* 0: clk26m */
+ /* CLK_CFG_6 */
+ mux_set_sel(&muxes[TOP_ATB_SEL], 1); /* 1: mainpll_d2_d2 */
+ mux_set_sel(&muxes[TOP_PWRMCU_SEL], 2); /* 2: mainpll_d2_d2 */
+ mux_set_sel(&muxes[TOP_DPI0_SEL], 1); /* 1: tvdpll_d2 */
+ mux_set_sel(&muxes[TOP_SCAM_SEL], 1); /* 1: mainpll_d5_d2 */
+ /* CLK_CFG_7 */
+ mux_set_sel(&muxes[TOP_DISP_PWM_SEL], 0); /* 0: clk26m */
+ mux_set_sel(&muxes[TOP_USB_TOP_SEL], 3); /* 3: univpll_d5_d2 */
+ mux_set_sel(&muxes[TOP_SSUSB_XHCI_SEL], 3); /* 3: univpll_d5_d2 */
+ mux_set_sel(&muxes[TOP_SPM_SEL], 1); /* 1: mainpll_d2_d8 */
+ /* CLK_CFG_8 */
+ mux_set_sel(&muxes[TOP_I2C_SEL], 2); /* 2: univpll_d5_d2 */
+ mux_set_sel(&muxes[TOP_SCP_SEL], 1); /* 1: univpll_d2_d8 */
+ mux_set_sel(&muxes[TOP_SENINF_SEL], 1); /* 1: univpll_d2_d2 */
+ mux_set_sel(&muxes[TOP_DXCC_SEL], 1); /* 1: mainpll_d2_d2 */
+ /* CLK_CFG_9 */
+ mux_set_sel(&muxes[TOP_AUD_ENGEN1_SEL], 3); /* 3: apll1_d8 */
+ mux_set_sel(&muxes[TOP_AUD_ENGEN2_SEL], 3); /* 3: apll2_d8 */
+ mux_set_sel(&muxes[TOP_AES_UFSFDE_SEL], 3); /* 3: mainpll_d3 */
+ mux_set_sel(&muxes[TOP_UFS_SEL], 1); /* 1: mainpll_d2_d4 */
+ /* CLK_CFG_10 */
+ mux_set_sel(&muxes[TOP_AUD_1_SEL], 1); /* 1: apll1_ck */
+ mux_set_sel(&muxes[TOP_AUD_2_SEL], 1); /* 1: apll2_ck */
+
+ /* enable [14] dramc_pll104m_ck */
+ setbits_le32(&mt8183_topckgen->clk_misc_cfg_0, 1 << 14);
+
+ /**************
+ * MTCMOS
+ ***************/
+
+ mtcmos_display_power_on();
+ mtcmos_display_bus_prot();
+ mtcmos_audio_power_on();
+
+ /**************
+ * SUBSYS CG
+ ***************/
+
+ write32(&mt8183_infracfg->module_sw_cg_0_clr, 0xDBEFFF7F);
+ write32(&mt8183_infracfg->module_sw_cg_1_clr, 0xDF9F7FF7);
+ write32(&mt8183_infracfg->module_sw_cg_1_set, 0x18000000);
+ write32(&mt8183_infracfg->module_sw_cg_2_clr, 0x7FFC07DD);
+ write32(&mt8183_infracfg->module_sw_cg_3_clr, 0x01FF01FF);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c
Gerrit-Change-Number: 27031
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Hsieh <tristan.shieh at mediatek.com>
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