<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27031">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: add pll and clock init support<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=the refactored code works fine on the new platform (with the rest<br> of the patches applied) and Elm platform<br><br>Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c<br>Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/Makefile.inc<br>A src/soc/mediatek/mt8183/bootblock.c<br>M src/soc/mediatek/mt8183/include/soc/addressmap.h<br>A src/soc/mediatek/mt8183/include/soc/mcucfg.h<br>A src/soc/mediatek/mt8183/include/soc/pll.h<br>A src/soc/mediatek/mt8183/pll.c<br>6 files changed, 1,137 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27031/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>index e827cd8..49c88ef 100644</span><br><span>--- a/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>@@ -1,7 +1,9 @@</span><br><span> ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span> bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c</span><br><span> bootblock-y += ../common/mtcmos.c mtcmos_extend.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += pll.c</span><br><span> bootblock-$(CONFIG_SPI_FLASH) += spi.c</span><br><span> bootblock-y += ../common/timer.c</span><br><span> ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)</span><br><span>diff --git a/src/soc/mediatek/mt8183/bootblock.c b/src/soc/mediatek/mt8183/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e4c331e</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/bootblock.c</span><br><span>@@ -0,0 +1,22 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pll.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ mt_pll_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>index 251e7f7..b616aac 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>@@ -17,14 +17,17 @@</span><br><span> #define __SOC_MEDIATEK_MT8183_INCLUDE_SOC_ADDRESSMAP_H__</span><br><span> </span><br><span> enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MCUCFG_BASE = 0x0C530000,</span><br><span> IO_PHYS = 0x10000000,</span><br><span> DDR_BASE = 0x40000000</span><br><span> };</span><br><span> </span><br><span> enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CKSYS_BASE = IO_PHYS,</span><br><span> INFRACFG_AO_BASE = IO_PHYS + 0x00001000,</span><br><span> SPM_BASE = IO_PHYS + 0x00006000,</span><br><span> GPT_BASE = IO_PHYS + 0x00008000,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_BASE = IO_PHYS + 0x0000C000,</span><br><span> UART0_BASE = IO_PHYS + 0x01002000,</span><br><span> SMI_BASE = IO_PHYS + 0x04019000,</span><br><span> };</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/mcucfg.h b/src/soc/mediatek/mt8183/include/soc/mcucfg.h</span><br><span>new file mode 100644</span><br><span>index 0000000..0a1232a</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/mcucfg.h</span><br><span>@@ -0,0 +1,386 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_MT8183_MCUCFG_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_MT8183_MCUCFG_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mt8183_mcucfg_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_cache_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_mem_delsel0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_mem_delsel1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cache_mem_delsel0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cache_mem_delsel1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_axi_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_misc_config9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_cfg_dis;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_clken_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_rst_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_misc_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_dbg_pwr_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_rw_rsvd0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_rw_rsvd1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ro_rsvd;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_l2_cache_parity1_rdata;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_l2_cache_parity2_rdata;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved4[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_rgu_dcm_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca53_specific_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_esr_case;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_esr_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_esr_trig_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved5[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ses_cg_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved6[216];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_dbg_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved7[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_ca7l_ir_mon;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved8[32];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_dfd_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_cnt_l;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_cnt_h;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 misccfg_ro_rsvd;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved9[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_gpu;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_psys;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_mp1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_mp0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_dbg_monitor_mp2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved10[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_op_arid_mp0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_op_arid_mp1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dvm_op_arid_mp2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved11[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s6_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved12[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_rst_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_dbg_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_dbg_flag;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_ca7l_ir_mon;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved13[32];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_dbg_mon_sel_a;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_dbg_mon;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 misccfg_sec_vio_status0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 misccfg_sec_vio_status1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_top_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m0_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m1_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m2_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s1_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s2_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s3_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s4_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m0_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m1_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_m2_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s1_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s2_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s3_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s4_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_tra_dbg_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s5_if_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_s5_tra_debug;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gic500_int_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 core_rst_en_latch;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved14[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dbg_core_ret;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_config_a;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_config1_a;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_gic_peribase_a;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_pinmux;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_range0_start;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_range0_end;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_range_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 l2c_mm_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved15[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 aclken_div;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pclken_div;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 l2c_sram_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_jit_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_addrmap;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_periphbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_nevntcntovfl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_acel_s1_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_bus_fabric_dcm_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcu_misc_dcm_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 xgpt_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 xgpt_idx;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved16[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_rw_rsvd0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcusys_rw_rsvd1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved17[13];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gic500_delsel_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 etb_delsel_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 etb_rst_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved18[13];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_secur_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_gen_timer_reset_mask_7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved19[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_cci_adb400_dcm_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_sync_dcm_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved20[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_sync_dcm_cluster_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sw_udi;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved21[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gic_sync_dcm;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 big_dbg_pwr_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gic_cpu_periphbase;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 axi_cpu_config;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved22[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_sys_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_sys_ctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_sys_ctrl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_sys_ctrl4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_dbg_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pwrmcu_apb2to1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved23[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_spmc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved24[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_spmc_sram_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved25[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_sw_rst_wait_cycle;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_pll_divider_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved26[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp2_pll_divider_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved27[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 bus_pll_divider_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved28[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clusterid_aff1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clusterid_aff2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 hack_ice_rom_table_access;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp_top_mem_delay_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 l2c_cfg_mp0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved29[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 l2c_cfg_mp2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved30[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt0to1_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt2to3_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt4to5_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt6to7_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt0to3_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_cnt4to7_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_ref_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_acc_cnt7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved31[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_id_ext_cnt0to3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_id_ext_cnt4to7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_mask_ext_cnt0to3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cci_bw_pmu_mask_ext_cnt4to7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved32[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 etb_acc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 etb_ck_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved33[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mp1_ocp_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved34[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_gic_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_gic_result;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mcsib_sf1_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mcsib_sf1_result;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mcsib_sf2_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_mcsib_sf2_result;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved35[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_rstb;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mbista_all_result;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved36[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved37[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp1_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved38[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp2_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp2_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved39[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gpu_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gpu_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved40[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 psys_hang_monitor_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 psys_hang_monitor_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved41[42];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en11;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en12;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en13;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en14;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en15;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en17;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en18;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sec_pol_ctl_en19;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved42[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl11;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl12;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl13;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl14;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl15;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl16;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl17;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl18;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 int_pol_ctl19;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved43[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_pwr_on;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_chain_legth_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_shift_clk_ratio;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_counter_return;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_sram_access;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_chain_length_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_chain_length_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_chain_length_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_test_so_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_test_so_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_num_of_test_so_gp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_test_so_over_64;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_mask_out;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_sw_ns_trigger;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_mcsib;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_mcsib_sel_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_sram_base_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dfd_internal_sram_delsel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsib_iccs_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved44[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcu_all_pwr_on_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_wfifo;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcsia_dcm_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved45[294];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcu_apb_base;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved46[384];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu_avg_stall_ratio;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_avg_stall_ratio_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_avg_stall_ratio_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_avg_stall_ratio_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_avg_stall_ratio_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_avg_stall_ratio_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_stall_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_stall_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_stall_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_stall_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu0_non_wfi_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu1_non_wfi_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu2_non_wfi_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_cpu3_non_wfi_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved47[370];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_sparkvretcntrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_sparken;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_amuxsel;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cg_dis;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu0_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu1_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu2_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu3_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_spark_debug_overwrite;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved48[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu0_spmc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu1_spmc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu2_spmc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpusys0_cpu3_spmc_ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sesv3_rg_toggle;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved49[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_sync_dcm_cgavg_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_sync_dcm_cgavg_fact;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_sync_dcm_cgavg_rfact;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mp0_sync_dcm_cgavg;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_cache_mem_delsel0, 0x0024);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp_dbg_ctrl, 0x0404);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp_dfd_ctrl, 0x0490);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, dvm_op_arid_mp0, 0x04c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, cci_s6_if_debug, 0x04e0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp1_rst_status, 0x0500);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mcusys_dbg_mon_sel_a, 0x0590);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, dbg_core_ret, 0x05fc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, aclken_div, 0x0640);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mcusys_rw_rsvd0, 0x0684);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, gic500_delsel_ctl, 0x06c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp_gen_timer_reset_mask_secur_en, 0x0700);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp_cci_adb400_dcm_config, 0x0740);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mcsib_sys_ctrl1, 0x0770);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, bus_pll_divider_cfg, 0x07c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, clusterid_aff1, 0x07e0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, cci_bw_pmu_id_ext_cnt0to3, 0x0860);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, etb_acc_ctl, 0x08b0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mbista_mp1_ocp_con, 0x08c8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mbista_rstb, 0x08f0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_hang_monitor_ctrl0, 0x0900);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp1_hang_monitor_ctrl0, 0x0910);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp2_hang_monitor_ctrl0, 0x0920);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, gpu_hang_monitor_ctrl0, 0x0940);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, psys_hang_monitor_ctrl0, 0x0950);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, sec_pol_ctl_en0, 0x0a00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, int_pol_ctl0, 0x0a80);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, dfd_internal_ctl, 0x0b00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mcu_apb_base, 0x0ffc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_cpu_avg_stall_ratio, 0x1600);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, cpusys0_sparkvretcntrl, 0x1c00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, cpusys0_cpu0_spmc_ctl, 0x1c30);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg_ctrl, 0x1c60);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg, 0x1c6c);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_MT8183_MCUCFG_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h</span><br><span>new file mode 100644</span><br><span>index 0000000..42dd9d9</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/pll.h</span><br><span>@@ -0,0 +1,251 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_MEDIATEK_MT8183_PLL_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_MEDIATEK_MT8183_PLL_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mt8183_topckgen_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_mode;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_update;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_update1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[13];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_0_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_0_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_1_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_1_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_2_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_2_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved4[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_3_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_3_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved5[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_4_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_4_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved6[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_5_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_5_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved7[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_6_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_6_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved8[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_7_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_7_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved9[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_8_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_8_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved10[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_9_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_9_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved11[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_10_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_10_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved12[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_misc_cfg_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_misc_cfg_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_dbg_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved13[60];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_scp_cfg_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_scp_cfg_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved14[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk26cali_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk26cali_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved15[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cksta_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cksta_reg1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved16[50];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clkmon_clk_sel_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clkmon_k1_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved17[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_auddiv_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_auddiv_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_auddiv_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 aud_top_cfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 aud_top_mon;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_auddiv_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved18[50];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_pdn_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved19[63];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_extck_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved20[79];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_20;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_20_set;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clk_cfg_20_clr;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clk_cfg_0, 0x0040);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clk_misc_cfg_0, 0x0104);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clk_scp_cfg_0, 0x0200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clk26cali_0, 0x0220);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, cksta_reg, 0x0230);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clkmon_clk_sel_reg, 0x0300);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clk_auddiv_0, 0x0320);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clk_pdn_reg, 0x0400);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clk_extck_reg, 0x0500);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clk_cfg_20, 0x0640);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_topckgen_regs, clk_cfg_20_clr, 0x0648);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mt8183_apmixed_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_pll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_pll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_pll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_pll_con3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_pll_con4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_pll_con5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_pll_con6;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_pll_con7;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_pll_con8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clksq_stb_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_pwr_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_iso_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_iso_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_stb_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 div_stb_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_chg_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_test_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pll_test_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1[109];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_ll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_ll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_ll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_ll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_l_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_l_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_l_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 armpll_l_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mainpll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mainpll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mainpll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mainpll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 univpll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 univpll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 univpll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 univpll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfgpll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfgpll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfgpll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mfgpll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 msdcpll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 msdcpll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 msdcpll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 msdcpll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tvdpll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tvdpll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tvdpll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tvdpll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mmpll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mmpll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mmpll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mmpll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mpll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mpll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mpll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mpll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ccipll_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ccipll_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ccipll_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ccipll_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll1_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll1_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll1_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll1_con3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll1_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll2_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll2_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll2_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll2_con3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 apll2_pwr_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved2[78];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_auxadc_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_auxadc_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_auxadc_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_auxadc_con3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_auxadc_con4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_auxadc_con5;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved3[122];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ts_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ts_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ts_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved4[61];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ulposc_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ulposc_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ulposc2_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ulposc2_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved5[60];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_abist_mon_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_abist_mon_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_abist_mon_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ap_abist_mon_con3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 occscan_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 clkdiv_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 occscan_con1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 occscan_con2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mcu_occscan_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved6[55];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rsv_rw0_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rsv_rw1_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rsv_ro_con0;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_apmixed_regs, armpll_ll_con0, 0x0200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_apmixed_regs, ap_auxadc_con0, 0x0400);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_apmixed_regs, ts_con0, 0x0600);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_apmixed_regs, ulposc_con0, 0x0700);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_apmixed_regs, ap_abist_mon_con0, 0x0800);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_apmixed_regs, rsv_rw0_con0, 0x0900);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(mt8183_apmixed_regs, rsv_ro_con0, 0x0908);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8183_topckgen_regs *const mt8183_topckgen = (void *)CKSYS_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct mt8183_apmixed_regs *const mt8183_apmixed = (void *)APMIXED_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PLL rate */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ ARMPLL_LL_HZ = 1100 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ ARMPLL_L_HZ = 1200 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ CCIPLL_HZ = 598 * 2 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAINPLL_HZ = 1092 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ UNIVPLL_HZ = 1248UL * 2 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ MSDCPLL_HZ = 384 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ MMPLL_HZ = 3150UL * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ MFGPLL_HZ = 512 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ TVDPLL_HZ = 594 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ APLL1_HZ = 180633600,</span><br><span style="color: hsl(120, 100%, 40%);">+ APLL2_HZ = 196608 * KHz,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* top_div rate */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CLK26M_HZ = 26 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_pll_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_MT8183_PLL_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c</span><br><span>new file mode 100644</span><br><span>index 0000000..00a2fa8</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/pll.c</span><br><span>@@ -0,0 +1,473 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stddef.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/infracfg.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mcucfg.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mtcmos.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mtcmos_extend.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pll.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum mux_id {</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_AXI_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_MM_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_IMG_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_CAM_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_DSP_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_DSP1_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_DSP2_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_IPU_IF_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_MFG_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_MFG_52M_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_CAMTG_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_CAMTG2_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_CAMTG3_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_CAMTG4_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_UART_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_SPI_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_MSDC50_0_HCLK_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_MSDC50_0_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_MSDC30_1_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_MSDC30_2_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_AUDIO_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_AUD_INTBUS_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_PMICSPI_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_PWRAP_ULPOSC_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_ATB_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_PWRMCU_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_DPI0_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_SCAM_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_DISP_PWM_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_USB_TOP_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_SSUSB_XHCI_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_SPM_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_I2C_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_SCP_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_SENINF_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_DXCC_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_AUD_ENGEN1_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_AUD_ENGEN2_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_AES_UFSFDE_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_UFS_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_AUD_1_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_AUD_2_SEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TOP_NR_MUX</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOPCKGEN_REG(x) (CKSYS_BASE + offsetof(struct mt8183_topckgen_regs, x))</span><br><span style="color: hsl(120, 100%, 40%);">+#define APMIXED_REG(x) (APMIXED_BASE + offsetof(struct mt8183_apmixed_regs, x))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mux {</span><br><span style="color: hsl(120, 100%, 40%);">+ void *reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mux_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mux_width;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *upd_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 upd_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MUX(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift) \</span><br><span style="color: hsl(120, 100%, 40%);">+ [_id] = { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .reg = (void *)TOPCKGEN_REG(_reg), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .mux_shift = _mux_shift, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .mux_width = _mux_width, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .upd_reg = (void *)TOPCKGEN_REG(_upd_reg), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .upd_shift = _upd_shift, \</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct mux muxes[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_AXI_SEL, clk_cfg_0, 0, 2, clk_cfg_update, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_MM_SEL, clk_cfg_0, 8, 3, clk_cfg_update, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_IMG_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_CAM_SEL, clk_cfg_0, 24, 4, clk_cfg_update, 3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_DSP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_DSP1_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_DSP2_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_IPU_IF_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_MFG_SEL, clk_cfg_2, 0, 2, clk_cfg_update, 8),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_MFG_52M_SEL, clk_cfg_2, 8, 2, clk_cfg_update, 9),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_CAMTG_SEL, clk_cfg_2, 16, 3, clk_cfg_update, 10),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_CAMTG2_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_CAMTG3_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_CAMTG4_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_UART_SEL, clk_cfg_3, 16, 1, clk_cfg_update, 14),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_SPI_SEL, clk_cfg_3, 24, 2, clk_cfg_update, 15),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_MSDC50_0_HCLK_SEL, clk_cfg_4, 0, 2, clk_cfg_update, 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_MSDC50_0_SEL, clk_cfg_4, 8, 3, clk_cfg_update, 17),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_MSDC30_1_SEL, clk_cfg_4, 16, 3, clk_cfg_update, 18),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_MSDC30_2_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_AUDIO_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_AUD_INTBUS_SEL, clk_cfg_5, 8, 2, clk_cfg_update, 21),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_PMICSPI_SEL, clk_cfg_5, 16, 2, clk_cfg_update, 22),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_PWRAP_ULPOSC_SEL, clk_cfg_5, 24, 2, clk_cfg_update, 23),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_ATB_SEL, clk_cfg_6, 0, 2, clk_cfg_update, 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_PWRMCU_SEL, clk_cfg_6, 8, 3, clk_cfg_update, 25),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_DPI0_SEL, clk_cfg_6, 16, 4, clk_cfg_update, 26),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_SCAM_SEL, clk_cfg_6, 24, 1, clk_cfg_update, 27),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_DISP_PWM_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_USB_TOP_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_SSUSB_XHCI_SEL, clk_cfg_7, 16, 2, clk_cfg_update, 30),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_SPM_SEL, clk_cfg_7, 24, 1, clk_cfg_update1, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_I2C_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_SCP_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_SENINF_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 3),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_DXCC_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 4),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_9 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_AUD_ENGEN1_SEL, clk_cfg_9, 0, 2, clk_cfg_update1, 5),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_AUD_ENGEN2_SEL, clk_cfg_9, 8, 2, clk_cfg_update1, 6),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_AES_UFSFDE_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 7),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_UFS_SEL, clk_cfg_9, 24, 2, clk_cfg_update1, 8),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_AUD_1_SEL, clk_cfg_10, 0, 1, clk_cfg_update1, 9),</span><br><span style="color: hsl(120, 100%, 40%);">+ MUX(TOP_AUD_2_SEL, clk_cfg_10, 8, 1, clk_cfg_update1, 10),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mux_set_sel(const struct mux *mux, u32 sel)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask = GENMASK(mux->mux_width - 1, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 val = read32(mux->reg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ val &= ~(mask << mux->mux_shift);</span><br><span style="color: hsl(120, 100%, 40%);">+ val |= (sel & mask) << mux->mux_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(mux->reg, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(mux->upd_reg, 1 << mux->upd_shift);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_PWR_ON (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_EN (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_ISO (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_RSTB (1 << 24)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MMPLL_RSTB (1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_PCW_CHG (1 << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL_POSTDIV_MASK 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCW_INTEGER_BITS 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum pll_id {</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_ARMPLL_LL,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_ARMPLL_L,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_CCIPLL,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_MAINPLL,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_UNIVPLL,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_MSDCPLL,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_MMPLL,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_MFGPLL,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_TVDPLL,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_APLL1,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_APLL2,</span><br><span style="color: hsl(120, 100%, 40%);">+ APMIXED_NR_PLL</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pll_div_rate[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 3800UL * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1248 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 624 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 384 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 200 * MHz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct pll {</span><br><span style="color: hsl(120, 100%, 40%);">+ void *reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *pwr_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rstb;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pcwbits;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *div_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 div_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *pcw_reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pcw_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 *div_rate;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \</span><br><span style="color: hsl(120, 100%, 40%);">+ _pcw_reg, _pcw_shift, _div_rate) \</span><br><span style="color: hsl(120, 100%, 40%);">+ [_id] = { \</span><br><span style="color: hsl(120, 100%, 40%);">+ .reg = (void *)APMIXED_REG(_reg), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pwr_reg = (void *)APMIXED_REG(_pwr_reg), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .rstb = _rstb, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pcwbits = _pcwbits, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .div_reg = (void *)APMIXED_REG(_div_reg), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .div_shift = _div_shift, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pcw_reg = (void *)APMIXED_REG(_pcw_reg), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .pcw_shift = _pcw_shift, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .div_rate = _div_rate, \</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pll plls[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_pwr_con0, PLL_RSTB, 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ armpll_ll_con1, 24, armpll_ll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_ARMPLL_L, armpll_l_con0, armpll_l_pwr_con0, PLL_RSTB, 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ armpll_l_con1, 24, armpll_l_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_pwr_con0, PLL_RSTB, 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ ccipll_con1, 24, ccipll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0, PLL_RSTB, 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ mainpll_con1, 24, mainpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0, PLL_RSTB, 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ univpll_con1, 24, univpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0, 0, 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ msdcpll_con1, 24, msdcpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0, MMPLL_RSTB, 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ mmpll_con1, 24, mmpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_pwr_con0, 0, 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ mfgpll_con1, 24, mfgpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0, 0, 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ tvdpll_con1, 24, tvdpll_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0, 0, 32,</span><br><span style="color: hsl(120, 100%, 40%);">+ apll1_con0, 1, apll1_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+ PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0, 0, 32,</span><br><span style="color: hsl(120, 100%, 40%);">+ apll2_con0, 1, apll2_con1, 0, pll_div_rate),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set postdiv */</span><br><span style="color: hsl(120, 100%, 40%);">+ val = read32(pll->div_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ val &= ~(PLL_POSTDIV_MASK << pll->div_shift);</span><br><span style="color: hsl(120, 100%, 40%);">+ val |= postdiv << pll->div_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* postdiv and pcw need to set at the same time if on same register */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pll->div_reg != pll->pcw_reg) {</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pll->div_reg, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = read32(pll->pcw_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set pcw */</span><br><span style="color: hsl(120, 100%, 40%);">+ val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);</span><br><span style="color: hsl(120, 100%, 40%);">+ val |= pcw << pll->pcw_shift;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pll->div_reg == pll->pcw_reg) {</span><br><span style="color: hsl(120, 100%, 40%);">+ val |= PLL_PCW_CHG;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pll->pcw_reg, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pll->pcw_reg, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ val = read32(pll->div_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ val |= PLL_PCW_CHG;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pll->div_reg, val);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 freq)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 fin_hz = CLK26M_HZ;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 *div_rate = pll->div_rate;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(freq <= div_rate[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(freq >= 1 * GHz / 16);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (val = 1; div_rate[val] != 0; val++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (freq > div_rate[val])</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ val--;</span><br><span style="color: hsl(120, 100%, 40%);">+ *postdiv = val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */</span><br><span style="color: hsl(120, 100%, 40%);">+ val += pll->pcwbits - PCW_INTEGER_BITS;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *pcw = ((u64)freq << val) / fin_hz;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int pll_set_rate(const struct pll *pll, u32 rate)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pcw = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 postdiv;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_calc_values(pll, &pcw, &postdiv, rate);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate_regs(pll, pcw, postdiv);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_pll_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable univpll & mainpll div */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mt8183_apmixed->ap_pll_con2, 0x1FFE << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable clock square1 low-pass filter */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mt8183_apmixed->ap_pll_con0, 0x2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*************</span><br><span style="color: hsl(120, 100%, 40%);">+ * xPLL PWR ON</span><br><span style="color: hsl(120, 100%, 40%);">+ **************/</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < APMIXED_NR_PLL; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(100);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /******************</span><br><span style="color: hsl(120, 100%, 40%);">+ * xPLL ISO Disable</span><br><span style="color: hsl(120, 100%, 40%);">+ *******************/</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < APMIXED_NR_PLL; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(plls[i].pwr_reg, PLL_ISO);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(50);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /********************</span><br><span style="color: hsl(120, 100%, 40%);">+ * xPLL Frequency Set</span><br><span style="color: hsl(120, 100%, 40%);">+ *********************/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_ARMPLL_LL], ARMPLL_LL_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_ARMPLL_L], ARMPLL_L_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_CCIPLL], CCIPLL_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_MAINPLL], MAINPLL_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_UNIVPLL], UNIVPLL_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_MSDCPLL], MSDCPLL_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_MMPLL], MMPLL_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_MFGPLL], MFGPLL_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_TVDPLL], TVDPLL_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_APLL1], APLL1_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+ pll_set_rate(&plls[APMIXED_APLL2], APLL2_HZ);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /********************</span><br><span style="color: hsl(120, 100%, 40%);">+ * AUDPLL Tuner Frequency Set</span><br><span style="color: hsl(120, 100%, 40%);">+ *********************/</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_apmixed->apll1_con2,</span><br><span style="color: hsl(120, 100%, 40%);">+ read32(&mt8183_apmixed->apll1_con1) + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_apmixed->apll2_con2,</span><br><span style="color: hsl(120, 100%, 40%);">+ read32(&mt8183_apmixed->apll2_con1) + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /***********************</span><br><span style="color: hsl(120, 100%, 40%);">+ * xPLL Frequency Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ ************************/</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < APMIXED_NR_PLL; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(plls[i].reg, PLL_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(50); /* wait for PLL stable */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /***************</span><br><span style="color: hsl(120, 100%, 40%);">+ * xPLL DIV RSTB</span><br><span style="color: hsl(120, 100%, 40%);">+ ****************/</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < APMIXED_NR_PLL; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (plls[i].rstb)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(plls[i].reg, plls[i].rstb);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /**************</span><br><span style="color: hsl(120, 100%, 40%);">+ * MCUCFG CLKMUX</span><br><span style="color: hsl(120, 100%, 40%);">+ ***************/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, 0x1f << 17,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8 << 17);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, 0x1f << 17,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8 << 17);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, 0x1f << 17,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8 << 17);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, 0x3 << 9, 1 << 9);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, 0x3 << 9, 1 << 9);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, 0x3 << 9, 1 << 9);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable infrasys DCM */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /************</span><br><span style="color: hsl(120, 100%, 40%);">+ * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!</span><br><span style="color: hsl(120, 100%, 40%);">+ *************/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_AXI_SEL], 2); /* 2: mainpll_d7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_MM_SEL], 1); /* 1: mmpll_d7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_IMG_SEL], 1); /* 1: mmpll_d6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_CAM_SEL], 1); /* 1: mainpll_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_DSP_SEL], 1); /* 1: mmpll_d6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_DSP1_SEL], 1); /* 1: mmpll_d6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_DSP2_SEL], 1); /* 1: mmpll_d6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_IPU_IF_SEL], 1); /* 1: mmpll_d6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_MFG_SEL], 1); /* 1: mfgpll_ck */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_MFG_52M_SEL], 3); /* 3: univpll_d3_d8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_CAMTG_SEL], 1); /* 1: univ_192m_d8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_CAMTG2_SEL], 1); /* 1: univ_192m_d8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_CAMTG3_SEL], 1); /* 1: univ_192m_d8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_CAMTG4_SEL], 1); /* 1: univ_192m_d8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_UART_SEL], 0); /* 0: clk26m */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_SPI_SEL], 1); /* 1: mainpll_d5_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_MSDC50_0_HCLK_SEL], 1); /* 1: mainpll_d2_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_MSDC50_0_SEL], 1); /* 1: msdcpll_ck */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_MSDC30_1_SEL], 4); /* 4: msdcpll_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_MSDC30_2_SEL], 1); /* 1: univpll_d3_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_AUDIO_SEL], 0); /* 0: clk26m */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_AUD_INTBUS_SEL], 1); /* 1: mainpll_d2_d4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_PMICSPI_SEL], 0); /* 0: clk26m */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_PWRAP_ULPOSC_SEL], 0); /* 0: clk26m */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_ATB_SEL], 1); /* 1: mainpll_d2_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_PWRMCU_SEL], 2); /* 2: mainpll_d2_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_DPI0_SEL], 1); /* 1: tvdpll_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_SCAM_SEL], 1); /* 1: mainpll_d5_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_DISP_PWM_SEL], 0); /* 0: clk26m */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_USB_TOP_SEL], 3); /* 3: univpll_d5_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_SSUSB_XHCI_SEL], 3); /* 3: univpll_d5_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_SPM_SEL], 1); /* 1: mainpll_d2_d8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_I2C_SEL], 2); /* 2: univpll_d5_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_SCP_SEL], 1); /* 1: univpll_d2_d8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_SENINF_SEL], 1); /* 1: univpll_d2_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_DXCC_SEL], 1); /* 1: mainpll_d2_d2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_9 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_AUD_ENGEN1_SEL], 3); /* 3: apll1_d8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_AUD_ENGEN2_SEL], 3); /* 3: apll2_d8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_AES_UFSFDE_SEL], 3); /* 3: mainpll_d3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_UFS_SEL], 1); /* 1: mainpll_d2_d4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLK_CFG_10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_AUD_1_SEL], 1); /* 1: apll1_ck */</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_set_sel(&muxes[TOP_AUD_2_SEL], 1); /* 1: apll2_ck */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable [14] dramc_pll104m_ck */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mt8183_topckgen->clk_misc_cfg_0, 1 << 14);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /**************</span><br><span style="color: hsl(120, 100%, 40%);">+ * MTCMOS</span><br><span style="color: hsl(120, 100%, 40%);">+ ***************/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mtcmos_display_power_on();</span><br><span style="color: hsl(120, 100%, 40%);">+ mtcmos_display_bus_prot();</span><br><span style="color: hsl(120, 100%, 40%);">+ mtcmos_audio_power_on();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /**************</span><br><span style="color: hsl(120, 100%, 40%);">+ * SUBSYS CG</span><br><span style="color: hsl(120, 100%, 40%);">+ ***************/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_infracfg->module_sw_cg_0_clr, 0xDBEFFF7F);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_infracfg->module_sw_cg_1_clr, 0xDF9F7FF7);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_infracfg->module_sw_cg_1_set, 0x18000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_infracfg->module_sw_cg_2_clr, 0x7FFC07DD);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_infracfg->module_sw_cg_3_clr, 0x01FF01FF);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27031">change 27031</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c </div>
<div style="display:none"> Gerrit-Change-Number: 27031 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>