[coreboot-gerrit] Change in coreboot[master]: google/fizz: fix LAN driver chip_info attachment

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27012


Change subject: google/fizz: fix LAN driver chip_info attachment
......................................................................

google/fizz: fix LAN driver chip_info attachment

As a result of commit:
[711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device

fizz's chip_info for the LAN driver is being overwritten/nulled, as the
LAN device is on function 2 (PCIe port 3), but the driver info was set
for the post-swapped PCIe port (1).
Move the driver chip_info to function 2/port 3, so that it follows the
PCI device function when swapped after FSP-s, and is correctly passed
to the LAN driver.

Test: boot google/fizz (teemo variant), check cbmem console and
verify ethernet MAC address and LED config correctly set.

Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/google/fizz/devicetree.cb
1 file changed, 5 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/27012/1

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 67828d1..0ac403e 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -429,17 +429,17 @@
 			end
 		end # I2C #5
 		device pci 19.2 off  end # I2C #4
-		device pci 1c.0 on # PCI Express Port 1
+		device pci 1c.0 on end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		# PCI Express Port 3 for LAN, will be swapped to port 1 by FSP
+		device pci 1c.2 on
 			chip drivers/net
 				register "customized_leds" = "0x0fa5"
 				register "wake" = "GPE0_PCI_EXP"
 				register "device_index" = "1"
 				device pci 00.0 on end
 			end
-		end # PCI Express Port 1
-		device pci 1c.1 off end # PCI Express Port 2
-		# PCI Express Port 3 for LAN, but will be swapped to port 1
-		device pci 1c.2 on end
+		end # PCI Express Port 3
 		device pci 1c.3 on
 			chip drivers/intel/wifi
 				register "wake" = "GPE0_PCI_EXP"

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec
Gerrit-Change-Number: 27012
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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