[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sun Jun 10 13:31:31 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27008
Change subject: soc/intel/denverton_ns: Get rid of device_t
......................................................................
soc/intel/denverton_ns: Get rid of device_t
Change-Id: I340a5fa101c0fac93788bc6f5bc6ca1ae006e072
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/soc/intel/broadwell/include/soc/xhci.h
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/xhci.c
M src/soc/intel/denverton_ns/bootblock/uart.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/include/soc/soc_util.h
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/soc_util.c
10 files changed, 53 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/27008/1
diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h
index cf1b135..33e4c2d 100644
--- a/src/soc/intel/broadwell/include/soc/xhci.h
+++ b/src/soc/intel/broadwell/include/soc/xhci.h
@@ -51,7 +51,7 @@
#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
#ifdef __SMM__
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
+void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
#endif
#endif
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 0b8a970..436d723 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -80,7 +80,7 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 75a63cf..fc20b88 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -140,7 +140,7 @@
}
/* Handler for XHCI controller on entry to S3/S4/S5 */
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
+void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index 9af42ee..919b481 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -32,7 +32,7 @@
{
register uint16_t reg16;
- device_t uart_dev = PCI_DEV(bus, dev, func);
+ pci_devfn_t uart_dev = PCI_DEV(bus, dev, func);
/* We're using MMIO for HSUARTs. This section is needed for logging
* from FSP only
diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c
index 7de0976..5f90185 100644
--- a/src/soc/intel/denverton_ns/csme_ie_kt.c
+++ b/src/soc/intel/denverton_ns/csme_ie_kt.c
@@ -56,7 +56,7 @@
compact_resources(dev);
}
-static void pci_csme_ie_kt_read_resources(device_t dev)
+static void pci_csme_ie_kt_read_resources(struct device *dev)
{
/**
* CSME/IE KT has 2 BARs to check:
diff --git a/src/soc/intel/denverton_ns/include/soc/soc_util.h b/src/soc/intel/denverton_ns/include/soc/soc_util.h
index 074ec16..45600fb 100644
--- a/src/soc/intel/denverton_ns/include/soc/soc_util.h
+++ b/src/soc/intel/denverton_ns/include/soc/soc_util.h
@@ -28,10 +28,17 @@
} silicon_revision;
/* soc_util.c */
-device_t get_hostbridge_dev(void);
-device_t get_lpc_dev(void);
-device_t get_pmc_dev(void);
-device_t get_smbus_dev(void);
+#if defined(__PRE_RAM__) || defined(__SMM__)
+pci_devfn_t get_hostbridge_dev(void);
+pci_devfn_t get_lpc_dev(void);
+pci_devfn_t get_pmc_dev(void);
+pci_devfn_t get_smbus_dev(void);
+#else
+struct device *get_hostbridge_dev(void);
+struct device *get_lpc_dev(void);
+struct device *get_pmc_dev(void);
+struct device *get_smbus_dev(void);
+#endif
uint32_t get_pciebase(void);
uint32_t get_pcielength(void);
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index 3fe41d2..0972dda 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -30,7 +30,7 @@
/* Returns base of requested region encoded in the system agent. */
static inline uintptr_t system_agent_region_base(size_t reg)
{
- device_t dev = SA_DEV_ROOT;
+ pci_devfn_t dev = SA_DEV_ROOT;
/* All regions concerned for have 1 MiB alignment. */
return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 105298e..51c7c59 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -50,7 +50,7 @@
static void early_pmc_init(void)
{
/* PMC (B0:D31:F2). */
- device_t dev = PCH_PMC_DEV;
+ pci_devfn_t dev = PCH_PMC_DEV;
/* Is PMC present */
if (pci_read_config16(dev, 0) == 0xffff) {
@@ -99,7 +99,7 @@
static void early_tco_init(void)
{
/* SMBUS (B0:D31:F4). */
- device_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
+ pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
/* Configure TCO base address */
if (pci_read_config16(dev, TCOBASE) == 0xffff) {
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index e434c1c..a1b9ca4 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -65,7 +65,7 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c
index 1626927..9d6ce9b 100644
--- a/src/soc/intel/denverton_ns/soc_util.c
+++ b/src/soc/intel/denverton_ns/soc_util.c
@@ -29,45 +29,51 @@
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
-device_t get_hostbridge_dev(void)
-{
#if defined(__PRE_RAM__) || defined(__SMM__)
+pci_devfn_t get_hostbridge_dev(void)
+{
return PCI_DEV(0, SA_DEV, SA_FUNC);
-#else
- return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC));
-#endif
}
-device_t get_lpc_dev(void)
+pci_devfn_t get_lpc_dev(void)
{
-#if defined(__PRE_RAM__) || defined(__SMM__)
+
return PCI_DEV(0, LPC_DEV, LPC_FUNC);
-#else
- return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
-#endif
}
-device_t get_pmc_dev(void)
+pci_devfn_t get_pmc_dev(void)
{
-#if defined(__PRE_RAM__) || defined(__SMM__)
return PCI_DEV(0, PMC_DEV, PMC_FUNC);
-#else
- return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC));
-#endif
}
-device_t get_smbus_dev(void)
+pci_devfn_t get_smbus_dev(void)
{
-#if defined(__PRE_RAM__) || defined(__SMM__)
return PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
#else
- return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC));
-#endif
+struct device *get_hostbridge_dev(void)
+{
+ return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC));
}
+struct device *get_lpc_dev(void)
+{
+ return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+}
+
+struct device *get_pmc_dev(void)
+{
+ return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC));
+}
+
+struct device *get_smbus_dev(void)
+{
+ return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC));
+}
+#endif
+
uint32_t get_pciebase(void)
{
- device_t dev;
+ struct device *dev;
u32 pciexbar_reg;
dev = get_hostbridge_dev();
@@ -99,7 +105,7 @@
uint32_t get_pcielength(void)
{
- device_t dev;
+ struct device *dev;
u32 pciexbar_reg;
dev = get_hostbridge_dev();
@@ -131,7 +137,7 @@
uint32_t get_tseg_memory(void)
{
- device_t dev = get_hostbridge_dev();
+ struct device *dev = get_hostbridge_dev();
if (!dev)
return 0;
@@ -141,7 +147,7 @@
uint32_t get_top_of_low_memory(void)
{
- device_t dev = get_hostbridge_dev();
+ struct device *dev = get_hostbridge_dev();
if (!dev)
return 0;
@@ -151,7 +157,7 @@
uint64_t get_top_of_upper_memory(void)
{
- device_t dev = get_hostbridge_dev();
+ struct device *dev = get_hostbridge_dev();
if (!dev)
return 0;
@@ -163,7 +169,7 @@
uint16_t get_pmbase(void)
{
- device_t dev = get_pmc_dev();
+ pci_devfn_t dev = get_pmc_dev();
if (!dev)
return 0;
@@ -173,7 +179,7 @@
uint16_t get_tcobase(void)
{
- device_t dev = get_smbus_dev();
+ pci_devfn_t dev = get_smbus_dev();
if (!dev)
return 0;
@@ -194,7 +200,7 @@
uint8_t silicon_stepping(void)
{
uint8_t revision_id;
- device_t dev = get_lpc_dev();
+ pci_devfn_t dev = get_lpc_dev();
if (!dev)
return 0;
--
To view, visit https://review.coreboot.org/27008
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I340a5fa101c0fac93788bc6f5bc6ca1ae006e072
Gerrit-Change-Number: 27008
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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