<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27008">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/denverton_ns: Get rid of device_t<br><br>Change-Id: I340a5fa101c0fac93788bc6f5bc6ca1ae006e072<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/broadwell/include/soc/xhci.h<br>M src/soc/intel/broadwell/smihandler.c<br>M src/soc/intel/broadwell/xhci.c<br>M src/soc/intel/denverton_ns/bootblock/uart.c<br>M src/soc/intel/denverton_ns/csme_ie_kt.c<br>M src/soc/intel/denverton_ns/include/soc/soc_util.h<br>M src/soc/intel/denverton_ns/memmap.c<br>M src/soc/intel/denverton_ns/romstage.c<br>M src/soc/intel/denverton_ns/smihandler.c<br>M src/soc/intel/denverton_ns/soc_util.c<br>10 files changed, 53 insertions(+), 40 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/27008/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h</span><br><span>index cf1b135..33e4c2d 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/xhci.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/xhci.h</span><br><span>@@ -51,7 +51,7 @@</span><br><span> #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span style="color: hsl(0, 100%, 40%);">-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);</span><br><span style="color: hsl(120, 100%, 40%);">+void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);</span><br><span> #endif</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c</span><br><span>index 0b8a970..436d723 100644</span><br><span>--- a/src/soc/intel/broadwell/smihandler.c</span><br><span>+++ b/src/soc/intel/broadwell/smihandler.c</span><br><span>@@ -80,7 +80,7 @@</span><br><span> for (slot = 0; slot < 0x20; slot++) {</span><br><span> for (func = 0; func < 8; func++) {</span><br><span> u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(bus, slot, func);</span><br><span> </span><br><span> val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span> </span><br><span>diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c</span><br><span>index 75a63cf..fc20b88 100644</span><br><span>--- a/src/soc/intel/broadwell/xhci.c</span><br><span>+++ b/src/soc/intel/broadwell/xhci.c</span><br><span>@@ -140,7 +140,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Handler for XHCI controller on entry to S3/S4/S5 */</span><br><span style="color: hsl(0, 100%, 40%);">-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)</span><br><span style="color: hsl(120, 100%, 40%);">+void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)</span><br><span> {</span><br><span> u16 reg16;</span><br><span> u32 reg32;</span><br><span>diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c</span><br><span>index 9af42ee..919b481 100644</span><br><span>--- a/src/soc/intel/denverton_ns/bootblock/uart.c</span><br><span>+++ b/src/soc/intel/denverton_ns/bootblock/uart.c</span><br><span>@@ -32,7 +32,7 @@</span><br><span> {</span><br><span> register uint16_t reg16;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- device_t uart_dev = PCI_DEV(bus, dev, func);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t uart_dev = PCI_DEV(bus, dev, func);</span><br><span> </span><br><span> /* We're using MMIO for HSUARTs. This section is needed for logging</span><br><span> * from FSP only</span><br><span>diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c</span><br><span>index 7de0976..5f90185 100644</span><br><span>--- a/src/soc/intel/denverton_ns/csme_ie_kt.c</span><br><span>+++ b/src/soc/intel/denverton_ns/csme_ie_kt.c</span><br><span>@@ -56,7 +56,7 @@</span><br><span> compact_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_csme_ie_kt_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_csme_ie_kt_read_resources(struct device *dev)</span><br><span> {</span><br><span> /**</span><br><span> * CSME/IE KT has 2 BARs to check:</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/soc_util.h b/src/soc/intel/denverton_ns/include/soc/soc_util.h</span><br><span>index 074ec16..45600fb 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/soc_util.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/soc_util.h</span><br><span>@@ -28,10 +28,17 @@</span><br><span> } silicon_revision;</span><br><span> </span><br><span> /* soc_util.c */</span><br><span style="color: hsl(0, 100%, 40%);">-device_t get_hostbridge_dev(void);</span><br><span style="color: hsl(0, 100%, 40%);">-device_t get_lpc_dev(void);</span><br><span style="color: hsl(0, 100%, 40%);">-device_t get_pmc_dev(void);</span><br><span style="color: hsl(0, 100%, 40%);">-device_t get_smbus_dev(void);</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__PRE_RAM__) || defined(__SMM__)</span><br><span style="color: hsl(120, 100%, 40%);">+pci_devfn_t get_hostbridge_dev(void);</span><br><span style="color: hsl(120, 100%, 40%);">+pci_devfn_t get_lpc_dev(void);</span><br><span style="color: hsl(120, 100%, 40%);">+pci_devfn_t get_pmc_dev(void);</span><br><span style="color: hsl(120, 100%, 40%);">+pci_devfn_t get_smbus_dev(void);</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+struct device *get_hostbridge_dev(void);</span><br><span style="color: hsl(120, 100%, 40%);">+struct device *get_lpc_dev(void);</span><br><span style="color: hsl(120, 100%, 40%);">+struct device *get_pmc_dev(void);</span><br><span style="color: hsl(120, 100%, 40%);">+struct device *get_smbus_dev(void);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> uint32_t get_pciebase(void);</span><br><span> uint32_t get_pcielength(void);</span><br><span>diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c</span><br><span>index 3fe41d2..0972dda 100644</span><br><span>--- a/src/soc/intel/denverton_ns/memmap.c</span><br><span>+++ b/src/soc/intel/denverton_ns/memmap.c</span><br><span>@@ -30,7 +30,7 @@</span><br><span> /* Returns base of requested region encoded in the system agent. */</span><br><span> static inline uintptr_t system_agent_region_base(size_t reg)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = SA_DEV_ROOT;</span><br><span> </span><br><span> /* All regions concerned for have 1 MiB alignment. */</span><br><span> return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);</span><br><span>diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c</span><br><span>index 105298e..51c7c59 100644</span><br><span>--- a/src/soc/intel/denverton_ns/romstage.c</span><br><span>+++ b/src/soc/intel/denverton_ns/romstage.c</span><br><span>@@ -50,7 +50,7 @@</span><br><span> static void early_pmc_init(void)</span><br><span> {</span><br><span> /* PMC (B0:D31:F2). */</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_PMC_DEV;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_PMC_DEV;</span><br><span> </span><br><span> /* Is PMC present */</span><br><span> if (pci_read_config16(dev, 0) == 0xffff) {</span><br><span>@@ -99,7 +99,7 @@</span><br><span> static void early_tco_init(void)</span><br><span> {</span><br><span> /* SMBUS (B0:D31:F4). */</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);</span><br><span> </span><br><span> /* Configure TCO base address */</span><br><span> if (pci_read_config16(dev, TCOBASE) == 0xffff) {</span><br><span>diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c</span><br><span>index e434c1c..a1b9ca4 100644</span><br><span>--- a/src/soc/intel/denverton_ns/smihandler.c</span><br><span>+++ b/src/soc/intel/denverton_ns/smihandler.c</span><br><span>@@ -65,7 +65,7 @@</span><br><span> for (slot = 0; slot < 0x20; slot++) {</span><br><span> for (func = 0; func < 8; func++) {</span><br><span> u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(bus, slot, func);</span><br><span> </span><br><span> val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span> </span><br><span>diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c</span><br><span>index 1626927..9d6ce9b 100644</span><br><span>--- a/src/soc/intel/denverton_ns/soc_util.c</span><br><span>+++ b/src/soc/intel/denverton_ns/soc_util.c</span><br><span>@@ -29,45 +29,51 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/systemagent.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-device_t get_hostbridge_dev(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span> #if defined(__PRE_RAM__) || defined(__SMM__)</span><br><span style="color: hsl(120, 100%, 40%);">+pci_devfn_t get_hostbridge_dev(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span> return PCI_DEV(0, SA_DEV, SA_FUNC);</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC));</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-device_t get_lpc_dev(void)</span><br><span style="color: hsl(120, 100%, 40%);">+pci_devfn_t get_lpc_dev(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined(__PRE_RAM__) || defined(__SMM__)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> return PCI_DEV(0, LPC_DEV, LPC_FUNC);</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-device_t get_pmc_dev(void)</span><br><span style="color: hsl(120, 100%, 40%);">+pci_devfn_t get_pmc_dev(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined(__PRE_RAM__) || defined(__SMM__)</span><br><span> return PCI_DEV(0, PMC_DEV, PMC_FUNC);</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC));</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-device_t get_smbus_dev(void)</span><br><span style="color: hsl(120, 100%, 40%);">+pci_devfn_t get_smbus_dev(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined(__PRE_RAM__) || defined(__SMM__)</span><br><span> return PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC));</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+struct device *get_hostbridge_dev(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+struct device *get_lpc_dev(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct device *get_pmc_dev(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct device *get_smbus_dev(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> uint32_t get_pciebase(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> u32 pciexbar_reg;</span><br><span> </span><br><span> dev = get_hostbridge_dev();</span><br><span>@@ -99,7 +105,7 @@</span><br><span> </span><br><span> uint32_t get_pcielength(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> u32 pciexbar_reg;</span><br><span> </span><br><span> dev = get_hostbridge_dev();</span><br><span>@@ -131,7 +137,7 @@</span><br><span> </span><br><span> uint32_t get_tseg_memory(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = get_hostbridge_dev();</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = get_hostbridge_dev();</span><br><span> </span><br><span> if (!dev)</span><br><span> return 0;</span><br><span>@@ -141,7 +147,7 @@</span><br><span> </span><br><span> uint32_t get_top_of_low_memory(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = get_hostbridge_dev();</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = get_hostbridge_dev();</span><br><span> </span><br><span> if (!dev)</span><br><span> return 0;</span><br><span>@@ -151,7 +157,7 @@</span><br><span> </span><br><span> uint64_t get_top_of_upper_memory(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = get_hostbridge_dev();</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = get_hostbridge_dev();</span><br><span> </span><br><span> if (!dev)</span><br><span> return 0;</span><br><span>@@ -163,7 +169,7 @@</span><br><span> </span><br><span> uint16_t get_pmbase(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = get_pmc_dev();</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = get_pmc_dev();</span><br><span> </span><br><span> if (!dev)</span><br><span> return 0;</span><br><span>@@ -173,7 +179,7 @@</span><br><span> </span><br><span> uint16_t get_tcobase(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = get_smbus_dev();</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = get_smbus_dev();</span><br><span> </span><br><span> if (!dev)</span><br><span> return 0;</span><br><span>@@ -194,7 +200,7 @@</span><br><span> uint8_t silicon_stepping(void)</span><br><span> {</span><br><span> uint8_t revision_id;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = get_lpc_dev();</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = get_lpc_dev();</span><br><span> </span><br><span> if (!dev)</span><br><span> return 0;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27008">change 27008</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27008"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I340a5fa101c0fac93788bc6f5bc6ca1ae006e072 </div>
<div style="display:none"> Gerrit-Change-Number: 27008 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>