[coreboot-gerrit] Change in coreboot[master]: mainboard: Use pci_devfn_t or pnp_devfn_t instead of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Fri Jun 8 19:03:00 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26984
Change subject: mainboard: Use pci_devfn_t or pnp_devfn_t instead of device_t
......................................................................
mainboard: Use pci_devfn_t or pnp_devfn_t instead of device_t
In romstage use pci_devfn_t or pnp_devfn_t.
Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/stout/chromeos.c
M src/mainboard/intel/baskingridge/chromeos.c
M src/mainboard/intel/cougar_canyon2/romstage.c
M src/mainboard/intel/d510mo/romstage.c
M src/mainboard/intel/emeraldlake2/chromeos.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/intel/galileo/gpio.c
M src/mainboard/samsung/lumpy/chromeos.c
M src/mainboard/samsung/stumpy/chromeos.c
M src/mainboard/tyan/s2912_fam10/get_bus_conf.c
15 files changed, 28 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/26984/1
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c
index 00a8d1f..f690efa 100644
--- a/src/mainboard/compulab/intense_pc/romstage.c
+++ b/src/mainboard/compulab/intense_pc/romstage.c
@@ -24,7 +24,7 @@
void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c
index 7412c62..ad4eab9 100644
--- a/src/mainboard/google/beltino/chromeos.c
+++ b/src/mainboard/google/beltino/chromeos.c
@@ -48,10 +48,11 @@
int get_write_protect_state(void)
{
- device_t dev;
#ifdef __PRE_RAM__
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@@ -59,10 +60,11 @@
int get_recovery_mode_switch(void)
{
- device_t dev;
#ifdef __PRE_RAM__
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index 42f6189..ab05512 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -37,7 +37,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
int lidswitch = 0;
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index f99fd6d..c7925fd 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -51,10 +51,11 @@
int get_write_protect_state(void)
{
- device_t dev;
#ifdef __PRE_RAM__
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@@ -62,10 +63,11 @@
int get_recovery_mode_switch(void)
{
- device_t dev;
#ifdef __PRE_RAM__
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index d2448eb..d3f1a8d 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -34,7 +34,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index 047e6a1..9a12c7e 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -97,11 +97,11 @@
int get_recovery_mode_switch(void)
{
#ifdef __PRE_RAM__
- device_t dev = PCI_DEV(0, 0x1f, 0);
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
#else
static int ec_in_rec_mode = 0;
static int ec_rec_flag_good = 0;
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
#endif
u8 ec_status = ec_read(EC_STATUS_REG);
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 5ed9e36..7300cb9 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -29,7 +29,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
if (!gpio_base)
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 96c22ea..54d2c04 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -51,7 +51,7 @@
static void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index b2044c1..77384ee 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -42,7 +42,7 @@
/* Early mainboard specific GPIO setup */
static void mb_gpio_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
/* Southbridge GPIOs. */
dev = PCI_DEV(0x0, 0x1f, 0x0);
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index eac995a..ae39c90 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -29,7 +29,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
if (!gpio_base)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index d23541f..7e2241f 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -42,7 +42,7 @@
void pch_enable_lpc(void)
{
- device_t dev = PCH_LPC_DEV;
+ pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c
index 857390e..025ba68 100644
--- a/src/mainboard/intel/galileo/gpio.c
+++ b/src/mainboard/intel/galileo/gpio.c
@@ -45,7 +45,7 @@
}
}
-void mainboard_gpio_i2c_init(device_t dev)
+void mainboard_gpio_i2c_init(pci_devfn_t dev)
{
const struct reg_script *script;
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index a287c74..59f4a3d 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -40,7 +40,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
u8 lid = ec_read(0x83);
@@ -91,7 +91,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@@ -103,7 +103,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
@@ -115,7 +115,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index 01d81d7..418a82c 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -37,7 +37,7 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
@@ -88,7 +88,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@@ -100,7 +100,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
@@ -112,7 +112,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index 29ab03d..5f07ae5 100644
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -65,7 +65,7 @@
unsigned apicid_base;
struct mb_sysconf_t *m;
- device_t dev;
+ pci_devfn_t dev;
int i;
if(get_bus_conf_done == 1) return; //do it only once
--
To view, visit https://review.coreboot.org/26984
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a
Gerrit-Change-Number: 26984
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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