<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26984">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard: Use pci_devfn_t or pnp_devfn_t instead of device_t<br><br>In romstage use pci_devfn_t or pnp_devfn_t.<br><br>Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/compulab/intense_pc/romstage.c<br>M src/mainboard/google/beltino/chromeos.c<br>M src/mainboard/google/butterfly/chromeos.c<br>M src/mainboard/google/jecht/chromeos.c<br>M src/mainboard/google/parrot/chromeos.c<br>M src/mainboard/google/stout/chromeos.c<br>M src/mainboard/intel/baskingridge/chromeos.c<br>M src/mainboard/intel/cougar_canyon2/romstage.c<br>M src/mainboard/intel/d510mo/romstage.c<br>M src/mainboard/intel/emeraldlake2/chromeos.c<br>M src/mainboard/intel/emeraldlake2/romstage.c<br>M src/mainboard/intel/galileo/gpio.c<br>M src/mainboard/samsung/lumpy/chromeos.c<br>M src/mainboard/samsung/stumpy/chromeos.c<br>M src/mainboard/tyan/s2912_fam10/get_bus_conf.c<br>15 files changed, 28 insertions(+), 24 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/26984/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c</span><br><span>index 00a8d1f..f690efa 100644</span><br><span>--- a/src/mainboard/compulab/intense_pc/romstage.c</span><br><span>+++ b/src/mainboard/compulab/intense_pc/romstage.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> </span><br><span> void pch_enable_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_LPC_DEV;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_LPC_DEV;</span><br><span> </span><br><span> /* Set COM1/COM2 decode range */</span><br><span> pci_write_config16(dev, LPC_IO_DEC, 0x0010);</span><br><span>diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c</span><br><span>index 7412c62..ad4eab9 100644</span><br><span>--- a/src/mainboard/google/beltino/chromeos.c</span><br><span>+++ b/src/mainboard/google/beltino/chromeos.c</span><br><span>@@ -48,10 +48,11 @@</span><br><span> </span><br><span> int get_write_protect_state(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span> #ifdef __PRE_RAM__</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;</span><br><span>@@ -59,10 +60,11 @@</span><br><span> </span><br><span> int get_recovery_mode_switch(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span> #ifdef __PRE_RAM__</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;</span><br><span>diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c</span><br><span>index 42f6189..ab05512 100644</span><br><span>--- a/src/mainboard/google/butterfly/chromeos.c</span><br><span>+++ b/src/mainboard/google/butterfly/chromeos.c</span><br><span>@@ -37,7 +37,7 @@</span><br><span> </span><br><span> void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;</span><br><span> </span><br><span> int lidswitch = 0;</span><br><span>diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c</span><br><span>index f99fd6d..c7925fd 100644</span><br><span>--- a/src/mainboard/google/jecht/chromeos.c</span><br><span>+++ b/src/mainboard/google/jecht/chromeos.c</span><br><span>@@ -51,10 +51,11 @@</span><br><span> </span><br><span> int get_write_protect_state(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span> #ifdef __PRE_RAM__</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;</span><br><span>@@ -62,10 +63,11 @@</span><br><span> </span><br><span> int get_recovery_mode_switch(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span> #ifdef __PRE_RAM__</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;</span><br><span>diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c</span><br><span>index d2448eb..d3f1a8d 100644</span><br><span>--- a/src/mainboard/google/parrot/chromeos.c</span><br><span>+++ b/src/mainboard/google/parrot/chromeos.c</span><br><span>@@ -34,7 +34,7 @@</span><br><span> </span><br><span> void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;</span><br><span> u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);</span><br><span> </span><br><span>diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c</span><br><span>index 047e6a1..9a12c7e 100644</span><br><span>--- a/src/mainboard/google/stout/chromeos.c</span><br><span>+++ b/src/mainboard/google/stout/chromeos.c</span><br><span>@@ -97,11 +97,11 @@</span><br><span> int get_recovery_mode_switch(void)</span><br><span> {</span><br><span> #ifdef __PRE_RAM__</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(0, 0x1f, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);</span><br><span> #else</span><br><span> static int ec_in_rec_mode = 0;</span><br><span> static int ec_rec_flag_good = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> #endif</span><br><span> </span><br><span> u8 ec_status = ec_read(EC_STATUS_REG);</span><br><span>diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c</span><br><span>index 5ed9e36..7300cb9 100644</span><br><span>--- a/src/mainboard/intel/baskingridge/chromeos.c</span><br><span>+++ b/src/mainboard/intel/baskingridge/chromeos.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> </span><br><span> void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;</span><br><span> </span><br><span> if (!gpio_base)</span><br><span>diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c</span><br><span>index 96c22ea..54d2c04 100644</span><br><span>--- a/src/mainboard/intel/cougar_canyon2/romstage.c</span><br><span>+++ b/src/mainboard/intel/cougar_canyon2/romstage.c</span><br><span>@@ -51,7 +51,7 @@</span><br><span> </span><br><span> static void pch_enable_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_LPC_DEV;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_LPC_DEV;</span><br><span> </span><br><span> /* Set COM1/COM2 decode range */</span><br><span> pci_write_config16(dev, LPC_IO_DEC, 0x0010);</span><br><span>diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c</span><br><span>index b2044c1..77384ee 100644</span><br><span>--- a/src/mainboard/intel/d510mo/romstage.c</span><br><span>+++ b/src/mainboard/intel/d510mo/romstage.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span> /* Early mainboard specific GPIO setup */</span><br><span> static void mb_gpio_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span> </span><br><span> /* Southbridge GPIOs. */</span><br><span> dev = PCI_DEV(0x0, 0x1f, 0x0);</span><br><span>diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c</span><br><span>index eac995a..ae39c90 100644</span><br><span>--- a/src/mainboard/intel/emeraldlake2/chromeos.c</span><br><span>+++ b/src/mainboard/intel/emeraldlake2/chromeos.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> </span><br><span> void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;</span><br><span> </span><br><span> if (!gpio_base)</span><br><span>diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>index d23541f..7e2241f 100644</span><br><span>--- a/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>+++ b/src/mainboard/intel/emeraldlake2/romstage.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span> </span><br><span> void pch_enable_lpc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_LPC_DEV;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCH_LPC_DEV;</span><br><span> </span><br><span> /* Set COM1/COM2 decode range */</span><br><span> pci_write_config16(dev, LPC_IO_DEC, 0x0010);</span><br><span>diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c</span><br><span>index 857390e..025ba68 100644</span><br><span>--- a/src/mainboard/intel/galileo/gpio.c</span><br><span>+++ b/src/mainboard/intel/galileo/gpio.c</span><br><span>@@ -45,7 +45,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void mainboard_gpio_i2c_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_gpio_i2c_init(pci_devfn_t dev)</span><br><span> {</span><br><span> const struct reg_script *script;</span><br><span> </span><br><span>diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c</span><br><span>index a287c74..59f4a3d 100644</span><br><span>--- a/src/mainboard/samsung/lumpy/chromeos.c</span><br><span>+++ b/src/mainboard/samsung/lumpy/chromeos.c</span><br><span>@@ -40,7 +40,7 @@</span><br><span> </span><br><span> void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);</span><br><span> u8 lid = ec_read(0x83);</span><br><span> </span><br><span>@@ -91,7 +91,7 @@</span><br><span> pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;</span><br><span>@@ -103,7 +103,7 @@</span><br><span> pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;</span><br><span>@@ -115,7 +115,7 @@</span><br><span> pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;</span><br><span>diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c</span><br><span>index 01d81d7..418a82c 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/chromeos.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/chromeos.c</span><br><span>@@ -37,7 +37,7 @@</span><br><span> </span><br><span> void fill_lb_gpios(struct lb_gpios *gpios)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);</span><br><span> </span><br><span> gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));</span><br><span>@@ -88,7 +88,7 @@</span><br><span> pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;</span><br><span>@@ -100,7 +100,7 @@</span><br><span> pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;</span><br><span>@@ -112,7 +112,7 @@</span><br><span> pci_devfn_t dev;</span><br><span> dev = PCI_DEV(0, 0x1f, 2);</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));</span><br><span> #endif</span><br><span> return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;</span><br><span>diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c</span><br><span>index 29ab03d..5f07ae5 100644</span><br><span>--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c</span><br><span>+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c</span><br><span>@@ -65,7 +65,7 @@</span><br><span> unsigned apicid_base;</span><br><span> struct mb_sysconf_t *m;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span> int i;</span><br><span> </span><br><span> if(get_bus_conf_done == 1) return; //do it only once</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26984">change 26984</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26984"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a </div>
<div style="display:none"> Gerrit-Change-Number: 26984 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>