[coreboot-gerrit] Change in coreboot[master]: nocturne: enable nvme

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/26933


Change subject: nocturne: enable nvme
......................................................................

nocturne: enable nvme

BUG=b:78122599
BRANCH=chromeos-2016.05
TEST='emerge-nocturne depthcharge coreboot chromeos-bootimage',
boot to kernel, and verify /dev/nvme* entries exist.
CQ-DEPEND=CL:1090070

Change-Id: I0070d33b1ed09bd1f51a680d92ddb7e2bcb1ebc2
Signed-off-by: Nick Vaccaro <nvaccaro at google.com>
---
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
1 file changed, 15 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/26933/1

diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 5b4c924..f746c08 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -160,6 +160,20 @@
 	register "PcieRpAdvancedErrorReporting[0]" = "1"
 	register "PcieRpLtrEnable[0]" = "1"
 
+        # Root port 9 (x2)
+        #  PcieRpEnable:                 Enable root port
+        #  PcieRpClkReqSupport:          Enable CLKREQ#
+        #  PcieRpClkReqNumber:           Uses SRCCLKREQ2#
+        #  PcieRpClkSrcNumber:           Uses 2
+        #  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
+        #  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
+        register "PcieRpEnable[8]" = "1"
+        register "PcieRpClkReqSupport[8]" = "1"
+        register "PcieRpClkReqNumber[8]" = "2"
+        register "PcieRpClkSrcNumber[8]" = "2"
+        register "PcieRpAdvancedErrorReporting[8]" = "1"
+        register "PcieRpLtrEnable[8]" = "1"
+
 	# USB 2.0
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Empty
@@ -326,7 +340,7 @@
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 off end # PCI Express Port 9
+		device pci 1d.0 on  end # PCI Express Port 9
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0070d33b1ed09bd1f51a680d92ddb7e2bcb1ebc2
Gerrit-Change-Number: 26933
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
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