<p>Nick Vaccaro has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26933">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nocturne: enable nvme<br><br>BUG=b:78122599<br>BRANCH=chromeos-2016.05<br>TEST='emerge-nocturne depthcharge coreboot chromeos-bootimage',<br>boot to kernel, and verify /dev/nvme* entries exist.<br>CQ-DEPEND=CL:1090070<br><br>Change-Id: I0070d33b1ed09bd1f51a680d92ddb7e2bcb1ebc2<br>Signed-off-by: Nick Vaccaro <nvaccaro@google.com><br>---<br>M src/mainboard/google/poppy/variants/nocturne/devicetree.cb<br>1 file changed, 15 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/26933/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>index 5b4c924..f746c08 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>@@ -160,6 +160,20 @@</span><br><span>  register "PcieRpAdvancedErrorReporting[0]" = "1"</span><br><span>         register "PcieRpLtrEnable[0]" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+        # Root port 9 (x2)</span><br><span style="color: hsl(120, 100%, 40%);">+        #  PcieRpEnable:                 Enable root port</span><br><span style="color: hsl(120, 100%, 40%);">+        #  PcieRpClkReqSupport:          Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+        #  PcieRpClkReqNumber:           Uses SRCCLKREQ2#</span><br><span style="color: hsl(120, 100%, 40%);">+        #  PcieRpClkSrcNumber:           Uses 2</span><br><span style="color: hsl(120, 100%, 40%);">+        #  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+        #  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+        register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+        register "PcieRpClkReqSupport[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+        register "PcieRpClkReqNumber[8]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+        register "PcieRpClkSrcNumber[8]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+        register "PcieRpAdvancedErrorReporting[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+        register "PcieRpLtrEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>         # USB 2.0</span><br><span>    register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"    # Type-C Port 1</span><br><span>      register "usb2_ports[1]" = "USB2_PORT_EMPTY"                # Empty</span><br><span>@@ -326,7 +340,7 @@</span><br><span>                device pci 1c.5 off end # PCI Express Port 6</span><br><span>                 device pci 1c.6 off end # PCI Express Port 7</span><br><span>                 device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(0, 100%, 40%);">-            device pci 1d.0 off end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+          device pci 1d.0 on  end # PCI Express Port 9</span><br><span>                 device pci 1d.1 off end # PCI Express Port 10</span><br><span>                device pci 1d.2 off end # PCI Express Port 11</span><br><span>                device pci 1d.3 off end # PCI Express Port 12</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26933">change 26933</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26933"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0070d33b1ed09bd1f51a680d92ddb7e2bcb1ebc2 </div>
<div style="display:none"> Gerrit-Change-Number: 26933 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>