[coreboot-gerrit] Change in coreboot[master]: Docs/relnotes: Add use of postcar stage on older Intel targets

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26889


Change subject: Docs/relnotes: Add use of postcar stage on older Intel targets
......................................................................

Docs/relnotes: Add use of postcar stage on older Intel targets

Change-Id: Icfb95112f3163273af29dc41f1e80f3866a7c04f
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M Documentation/releases/coreboot-4.9-relnotes.md
1 file changed, 13 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/26889/1

diff --git a/Documentation/releases/coreboot-4.9-relnotes.md b/Documentation/releases/coreboot-4.9-relnotes.md
index 788d695..0cfbc63 100644
--- a/Documentation/releases/coreboot-4.9-relnotes.md
+++ b/Documentation/releases/coreboot-4.9-relnotes.md
@@ -21,3 +21,16 @@
 ---------
 
 * Update IASL to version 10280531
+
+Legacy Intel CPUs
+-----------------
+
+* cpu/intel/car: split of cache as ram setup for postcar stage use
+* cpu/intel/car: Compute more things during runtime when setting up the cache
+  as ram
+
+Legacy Intel northbridge
+------------------------
+
+* cpu/intel/northbridge/{i945,gm45,x4x,pineview,nehalem,sandybridge,haswell}:
+  use postcar stage to tear down cache as ram and recover global varianbles

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icfb95112f3163273af29dc41f1e80f3866a7c04f
Gerrit-Change-Number: 26889
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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