<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26889">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Docs/relnotes: Add use of postcar stage on older Intel targets<br><br>Change-Id: Icfb95112f3163273af29dc41f1e80f3866a7c04f<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M Documentation/releases/coreboot-4.9-relnotes.md<br>1 file changed, 13 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/26889/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/releases/coreboot-4.9-relnotes.md b/Documentation/releases/coreboot-4.9-relnotes.md</span><br><span>index 788d695..0cfbc63 100644</span><br><span>--- a/Documentation/releases/coreboot-4.9-relnotes.md</span><br><span>+++ b/Documentation/releases/coreboot-4.9-relnotes.md</span><br><span>@@ -21,3 +21,16 @@</span><br><span> ---------</span><br><span> </span><br><span> * Update IASL to version 10280531</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Legacy Intel CPUs</span><br><span style="color: hsl(120, 100%, 40%);">+-----------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* cpu/intel/car: split of cache as ram setup for postcar stage use</span><br><span style="color: hsl(120, 100%, 40%);">+* cpu/intel/car: Compute more things during runtime when setting up the cache</span><br><span style="color: hsl(120, 100%, 40%);">+  as ram</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Legacy Intel northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* cpu/intel/northbridge/{i945,gm45,x4x,pineview,nehalem,sandybridge,haswell}:</span><br><span style="color: hsl(120, 100%, 40%);">+  use postcar stage to tear down cache as ram and recover global varianbles</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26889">change 26889</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26889"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icfb95112f3163273af29dc41f1e80f3866a7c04f </div>
<div style="display:none"> Gerrit-Change-Number: 26889 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>