[coreboot-gerrit] Change in coreboot[master]: [WIP]cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
Arthur Heymans (Code Review)
gerrit at coreboot.org
Tue Jun 5 11:28:54 CEST 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26859
Change subject: [WIP]cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
[WIP]cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
Already works but might be better to have an implementation of
normal/fallback in C_ENVIRONMENT_BOOTBLOCK...
This puts the cache as ram in the bootblock.
Tested on Google peppy (Acer C720)
Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
A src/cpu/intel/car/bootblock.c
A src/cpu/intel/car/bootblock.h
A src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S
M src/cpu/intel/car/romstage.c
M src/cpu/intel/haswell/Makefile.inc
A src/cpu/intel/haswell/bootblock_gcc.c
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/Makefile.inc
A src/northbridge/intel/haswell/bootblock_gcc.c
M src/southbridge/intel/lynxpoint/Makefile.inc
A src/southbridge/intel/lynxpoint/bootblock_gcc.c
M src/southbridge/intel/lynxpoint/early_pch.c
12 files changed, 494 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26859/1
diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c
new file mode 100644
index 0000000..e64073a
--- /dev/null
+++ b/src/cpu/intel/car/bootblock.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/intel/car/bootblock.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+ /* Call lib/bootblock.c main */
+ bootblock_main_with_timestamp(base_timestamp, NULL, 0);
+}
+
+static void enable_rom_caching(void)
+{
+ int mtrr = get_free_var_mtrr();
+
+ if (mtrr == -1)
+ return;
+
+ set_var_mtrr(mtrr, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+}
+
+void bootblock_soc_early_init(void)
+{
+ bootblock_early_cpu_init();
+ bootblock_early_northbridge_init();
+ bootblock_early_southbridge_init();
+}
+
+void bootblock_soc_init(void)
+{
+ enable_rom_caching();
+}
diff --git a/src/cpu/intel/car/bootblock.h b/src/cpu/intel/car/bootblock.h
new file mode 100644
index 0000000..5adfd87
--- /dev/null
+++ b/src/cpu/intel/car/bootblock.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_INTEL_CAR_BOOTBLOCK_H
+#define _CPU_INTEL_CAR_BOOTBLOCK_H
+
+void bootblock_early_cpu_init(void);
+void bootblock_early_northbridge_init(void);
+void bootblock_early_southbridge_init(void);
+
+#endif
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S b/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S
new file mode 100644
index 0000000..1c3b736
--- /dev/null
+++ b/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+#define CACHE_AS_RAM_SIZE (CONFIG_DCACHE_RAM_SIZE \
+ + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+#define NoEvictMod_MSR 0x2e0
+
+.global bootblock_pre_c_entry
+
+.code32
+bootblock_pre_c_entry:
+_cache_as_ram_setup:
+
+cache_as_ram:
+ post_code(0x20)
+
+ /* Send INIT IPI to all excluding ourself. */
+ movl $0x000C4500, %eax
+ movl $0xFEE00300, %esi
+ movl %eax, (%esi)
+
+ /* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+ movl (%esi), %eax
+ bt $12, %eax
+ jc wait_for_sipi
+
+ post_code(0x21)
+ /* Clean-up MTRR_DEF_TYPE_MSR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ xorl %eax, %eax
+ xorl %edx, %edx
+ wrmsr
+
+ post_code(0x22)
+ /* Clear/disable fixed MTRRs */
+ mov $fixed_mtrr_list_size, %ebx
+ xor %eax, %eax
+ xor %edx, %edx
+
+clear_fixed_mtrr:
+ add $-2, %ebx
+ movzwl fixed_mtrr_list(%ebx), %ecx
+ wrmsr
+ jnz clear_fixed_mtrr
+
+ /* Zero out all variable range MTRRs. */
+ movl $MTRR_CAP_MSR, %ecx
+ rdmsr
+ andl $0xff, %eax
+ shl $1, %eax
+ movl %eax, %edi
+ movl $0x200, %ecx
+ xorl %eax, %eax
+ xorl %edx, %edx
+clear_var_mtrrs:
+ wrmsr
+ add $1, %ecx
+ dec %edi
+ jnz clear_var_mtrrs
+
+ /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */
+ movl $0x80000008, %eax
+ cpuid
+ movb %al, %cl
+ sub $32, %cl
+ movl $1, %edx
+ shl %cl, %edx
+ subl $1, %edx
+
+ /* Preload high word of address mask (in %edx) for Variable
+ * MTRRs 0.
+ */
+addrsize_set_high:
+ xorl %eax, %eax
+ movl $MTRR_PHYS_MASK(0), %ecx
+ wrmsr
+
+
+ post_code(0x23)
+ /* Set Cache-as-RAM base address. */
+ movl $(MTRR_PHYS_BASE(0)), %ecx
+ movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ post_code(0x24)
+ /* Set Cache-as-RAM mask. */
+ movl $(MTRR_PHYS_MASK(0)), %ecx
+ rdmsr
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+ wrmsr
+
+ post_code(0x25)
+
+ /* Enable MTRR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ orl $MTRR_DEF_TYPE_EN, %eax
+ wrmsr
+
+ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+ movl %cr0, %eax
+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+ invd
+ movl %eax, %cr0
+
+ /* enable the 'no eviction' mode */
+ movl $NoEvictMod_MSR, %ecx
+ rdmsr
+ orl $1, %eax
+ andl $~2, %eax
+ wrmsr
+
+ /* Clear the cache memory region. This will also fill up the cache. */
+ movl $CACHE_AS_RAM_BASE, %esi
+ movl %esi, %edi
+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
+ xorl %eax, %eax
+ rep stosl
+
+ /* enable the 'no eviction run' state */
+ movl $NoEvictMod_MSR, %ecx
+ rdmsr
+ orl $3, %eax
+ wrmsr
+
+ post_code(0x26)
+ /* Enable Cache-as-RAM mode by disabling cache. */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ post_code(0x28)
+ /* Enable cache. */
+ movl %cr0, %eax
+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+ movl %eax, %cr0
+
+ /* Setup the stack. */
+ mov $_car_stack_end, %esp
+
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the two pushes below. */
+ andl $0xfffffff0, %esp
+ sub $8, %esp
+
+ /*push TSC value to stack*/
+ movd %mm2, %eax
+ pushl %eax /* tsc[63:32] */
+ movd %mm1, %eax
+ pushl %eax /* tsc[31:0] */
+
+before_romstage:
+ post_code(0x29)
+ /* Call romstage.c main function. */
+ call bootblock_c_entry
+
+ /* Should never see this postcode */
+ post_code(POST_DEAD_CODE)
+
+
+.Lhlt:
+ hlt
+ jmp .Lhlt
+
+fixed_mtrr_list:
+ .word MTRR_FIX_64K_00000
+ .word MTRR_FIX_16K_80000
+ .word MTRR_FIX_16K_A0000
+ .word MTRR_FIX_4K_C0000
+ .word MTRR_FIX_4K_C8000
+ .word MTRR_FIX_4K_D0000
+ .word MTRR_FIX_4K_D8000
+ .word MTRR_FIX_4K_E0000
+ .word MTRR_FIX_4K_E8000
+ .word MTRR_FIX_4K_F0000
+ .word MTRR_FIX_4K_F8000
+fixed_mtrr_list_size = . - fixed_mtrr_list
+
+_cache_as_ram_setup_end:
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index c36e046..1715fc5 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -65,3 +65,11 @@
/* Load the ramstage. */
run_ramstage();
}
+
+asmlinkage void car_stage_entry(void)
+{
+ unsigned long bist = 0;
+ console_init();
+ mainboard_romstage_entry(bist);
+ platform_enter_postcar();
+}
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index bbd98da..ed132d3 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -16,7 +16,14 @@
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
smm-y += monotonic_timer.c
+ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+else
+bootblock-y += ../car/non-evict/cache_as_ram_bootblock.S
+bootblock-y += ../car/bootblock.c
+bootblock-y += bootblock_gcc.c
+endif
+
postcar-y += ../car/non-evict/exit_car.S
subdirs-y += ../../x86/tsc
diff --git a/src/cpu/intel/haswell/bootblock_gcc.c b/src/cpu/intel/haswell/bootblock_gcc.c
new file mode 100644
index 0000000..7baa2a8
--- /dev/null
+++ b/src/cpu/intel/haswell/bootblock_gcc.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <arch/io.h>
+#include <halt.h>
+
+#include <cpu/intel/microcode/microcode.c>
+#include "haswell.h"
+
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <cpu/intel/car/bootblock.h>
+
+static void set_flex_ratio_to_tdp_nominal(void)
+{
+ msr_t flex_ratio, msr;
+ u32 soft_reset;
+ u8 nominal_ratio;
+
+ /* Check for Flex Ratio support */
+ flex_ratio = rdmsr(MSR_FLEX_RATIO);
+ if (!(flex_ratio.lo & FLEX_RATIO_EN))
+ return;
+
+ /* Check for >0 configurable TDPs */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ if (((msr.hi >> 1) & 3) == 0)
+ return;
+
+ /* Use nominal TDP ratio for flex ratio */
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ nominal_ratio = msr.lo & 0xff;
+
+ /* See if flex ratio is already set to nominal TDP ratio */
+ if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+ return;
+
+ /* Set flex ratio to nominal TDP ratio */
+ flex_ratio.lo &= ~0xff00;
+ flex_ratio.lo |= nominal_ratio << 8;
+ flex_ratio.lo |= FLEX_RATIO_LOCK;
+ wrmsr(MSR_FLEX_RATIO, flex_ratio);
+
+ /* Set flex ratio in soft reset data register bits 11:6.
+ * RCBA region is enabled in southbridge bootblock */
+ soft_reset = RCBA32(SOFT_RESET_DATA);
+ soft_reset &= ~(0x3f << 6);
+ soft_reset |= (nominal_ratio & 0x3f) << 6;
+ RCBA32(SOFT_RESET_DATA) = soft_reset;
+
+ /* Set soft reset control to use register value */
+ RCBA32_OR(SOFT_RESET_CTRL, 1);
+
+ /* Issue warm reset, will be "CPU only" due to soft reset data */
+ outb(0x0, 0xcf9);
+ outb(0x6, 0xcf9);
+ halt();
+}
+
+void bootblock_early_cpu_init(void)
+{
+ /* Set flex ratio and reset if needed */
+ set_flex_ratio_to_tdp_nominal();
+}
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 3a47195..9019a8b 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -23,6 +23,8 @@
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select POSTCAR_STAGE
select POSTCAR_CONSOLE
+ select C_ENVIRONMENT_BOOTBLOCK
+ select BOOTBLOCK_CONSOLE
if NORTHBRIDGE_INTEL_HASWELL
@@ -59,6 +61,13 @@
help
The amount of cache-as-ram region required by the reference code.
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
+
config HAVE_MRC
bool "Add a System Agent binary"
help
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 055c2a8..1566c73 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y)
+bootblock-y += bootblock_gcc.c
+
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
diff --git a/src/northbridge/intel/haswell/bootblock_gcc.c b/src/northbridge/intel/haswell/bootblock_gcc.c
new file mode 100644
index 0000000..e907bca
--- /dev/null
+++ b/src/northbridge/intel/haswell/bootblock_gcc.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/intel/car/bootblock.h>
+#include "haswell.h"
+
+void bootblock_early_northbridge_init(void)
+{
+ uint32_t reg;
+
+ /*
+ * The "io" variant of the config access is explicitly used to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
+ * to true. That way all subsequent non-explicit config accesses use
+ * MCFG. This code also assumes that bootblock_northbridge_init() is
+ * the first thing called in the non-asm boot block code. The final
+ * assumption is that no assembly code is using the
+ * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
+ *
+ * The PCIEXBAR is assumed to live in the memory mapped IO space under
+ * 4GiB.
+ */
+ reg = 0;
+ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg);
+ reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
+ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
+}
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 6abdf4d..2bd66a1 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
+bootblock-y += bootblock_gcc.c
+
ramstage-y += pch.c
ramstage-y += azalia.c
ramstage-y += lpc.c
diff --git a/src/southbridge/intel/lynxpoint/bootblock_gcc.c b/src/southbridge/intel/lynxpoint/bootblock_gcc.c
new file mode 100644
index 0000000..dd9e112
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/bootblock_gcc.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/intel/car/bootblock.h>
+#include "pch.h"
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(void)
+{
+ u8 reg8;
+ pci_devfn_t dev;
+
+ dev = PCI_DEV(0, 0x1f, 0);
+
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
+}
+
+
+static void map_rcba(void)
+{
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+
+ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+}
+
+static void enable_port80_on_lpc(void)
+{
+ /* Enable port 80 POST on LPC. The chipset does this by default,
+ * but it doesn't appear to hurt anything. */
+ u32 gcs = RCBA32(GCS);
+ gcs = gcs & ~0x4;
+ RCBA32(GCS) = gcs;
+}
+
+static void set_spi_speed(void)
+{
+ u32 fdod;
+ u8 ssfc;
+
+ /* Observe SPI Descriptor Component Section 0 */
+ SPIBAR32(FDOC) = 0x1000;
+
+ /* Extract the Write/Erase SPI Frequency from descriptor */
+ fdod = SPIBAR32(FDOD);
+ fdod >>= 24;
+ fdod &= 7;
+
+ /* Set Software Sequence frequency to match */
+ ssfc = SPIBAR8(SSFC + 2);
+ ssfc &= ~7;
+ ssfc |= fdod;
+ SPIBAR8(SSFC + 2) = ssfc;
+}
+
+void bootblock_early_southbridge_init(void)
+{
+ map_rcba();
+ enable_spi_prefetch();
+ enable_port80_on_lpc();
+ set_spi_speed();
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(RC) = (1 << 2);
+}
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index cb4bc7e..ae7299b 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -139,8 +139,6 @@
setup_pch_gpios(gpio_map);
#endif
- console_init();
-
pch_generic_setup();
/* Enable SMBus for reading SPDs. */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Gerrit-Change-Number: 26859
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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