<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26859">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK<br><br>Already works but might be better to have an implementation of<br>normal/fallback in C_ENVIRONMENT_BOOTBLOCK...<br><br>This puts the cache as ram in the bootblock.<br><br>Tested on Google peppy (Acer C720)<br><br>Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>A src/cpu/intel/car/bootblock.c<br>A src/cpu/intel/car/bootblock.h<br>A src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S<br>M src/cpu/intel/car/romstage.c<br>M src/cpu/intel/haswell/Makefile.inc<br>A src/cpu/intel/haswell/bootblock_gcc.c<br>M src/northbridge/intel/haswell/Kconfig<br>M src/northbridge/intel/haswell/Makefile.inc<br>A src/northbridge/intel/haswell/bootblock_gcc.c<br>M src/southbridge/intel/lynxpoint/Makefile.inc<br>A src/southbridge/intel/lynxpoint/bootblock_gcc.c<br>M src/southbridge/intel/lynxpoint/early_pch.c<br>12 files changed, 494 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26859/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e64073a</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/car/bootblock.c</span><br><span>@@ -0,0 +1,45 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Call lib/bootblock.c main */</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_main_with_timestamp(base_timestamp, NULL, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_rom_caching(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int mtrr = get_free_var_mtrr();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mtrr == -1)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ set_var_mtrr(mtrr, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_early_cpu_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_early_northbridge_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ bootblock_early_southbridge_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_soc_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_rom_caching();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/cpu/intel/car/bootblock.h b/src/cpu/intel/car/bootblock.h</span><br><span>new file mode 100644</span><br><span>index 0000000..5adfd87</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/car/bootblock.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _CPU_INTEL_CAR_BOOTBLOCK_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define _CPU_INTEL_CAR_BOOTBLOCK_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_cpu_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_northbridge_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_southbridge_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S b/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S</span><br><span>new file mode 100644</span><br><span>index 0000000..1c3b736</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/car/non-evict/cache_as_ram_bootblock.S</span><br><span>@@ -0,0 +1,201 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CACHE_AS_RAM_SIZE (CONFIG_DCACHE_RAM_SIZE \</span><br><span style="color: hsl(120, 100%, 40%);">+ + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NoEvictMod_MSR 0x2e0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.global bootblock_pre_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.code32</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock_pre_c_entry:</span><br><span style="color: hsl(120, 100%, 40%);">+_cache_as_ram_setup:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cache_as_ram:</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x20)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Send INIT IPI to all excluding ourself. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x000C4500, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0xFEE00300, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, (%esi)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* All CPUs need to be in Wait for SIPI state */</span><br><span style="color: hsl(120, 100%, 40%);">+wait_for_sipi:</span><br><span style="color: hsl(120, 100%, 40%);">+ movl (%esi), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ bt $12, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ jc wait_for_sipi</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x21)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clean-up MTRR_DEF_TYPE_MSR. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x22)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear/disable fixed MTRRs */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $fixed_mtrr_list_size, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+clear_fixed_mtrr:</span><br><span style="color: hsl(120, 100%, 40%);">+ add $-2, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ movzwl fixed_mtrr_list(%ebx), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ jnz clear_fixed_mtrr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Zero out all variable range MTRRs. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_CAP_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $0xff, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ shl $1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x200, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+clear_var_mtrrs:</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ add $1, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ dec %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ jnz clear_var_mtrrs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0x80000008, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuid</span><br><span style="color: hsl(120, 100%, 40%);">+ movb %al, %cl</span><br><span style="color: hsl(120, 100%, 40%);">+ sub $32, %cl</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $1, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ shl %cl, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ subl $1, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Preload high word of address mask (in %edx) for Variable</span><br><span style="color: hsl(120, 100%, 40%);">+ * MTRRs 0.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+addrsize_set_high:</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_PHYS_MASK(0), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x23)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Cache-as-RAM base address. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(MTRR_PHYS_BASE(0)), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x24)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Cache-as-RAM mask. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(MTRR_PHYS_MASK(0)), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x25)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable MTRR. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable cache (CR0.CD = 0, CR0.NW = 0). */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ invd</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable the 'no eviction' mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $~2, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear the cache memory region. This will also fill up the cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $CACHE_AS_RAM_BASE, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %esi, %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(CACHE_AS_RAM_SIZE >> 2), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ rep stosl</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable the 'no eviction run' state */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $3, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x26)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable Cache-as-RAM mode by disabling cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x28)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup the stack. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $_car_stack_end, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Need to align stack to 16 bytes at call instruction. Account for</span><br><span style="color: hsl(120, 100%, 40%);">+ the two pushes below. */</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $0xfffffff0, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+ sub $8, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*push TSC value to stack*/</span><br><span style="color: hsl(120, 100%, 40%);">+ movd %mm2, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %eax /* tsc[63:32] */</span><br><span style="color: hsl(120, 100%, 40%);">+ movd %mm1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %eax /* tsc[31:0] */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+before_romstage:</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x29)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Call romstage.c main function. */</span><br><span style="color: hsl(120, 100%, 40%);">+ call bootblock_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Should never see this postcode */</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.Lhlt:</span><br><span style="color: hsl(120, 100%, 40%);">+ hlt</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .Lhlt</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+fixed_mtrr_list:</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_64K_00000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_16K_80000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_16K_A0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_C0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_C8000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_D0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_D8000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_E0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_E8000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_F0000</span><br><span style="color: hsl(120, 100%, 40%);">+ .word MTRR_FIX_4K_F8000</span><br><span style="color: hsl(120, 100%, 40%);">+fixed_mtrr_list_size = . - fixed_mtrr_list</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+_cache_as_ram_setup_end:</span><br><span>diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c</span><br><span>index c36e046..1715fc5 100644</span><br><span>--- a/src/cpu/intel/car/romstage.c</span><br><span>+++ b/src/cpu/intel/car/romstage.c</span><br><span>@@ -65,3 +65,11 @@</span><br><span> /* Load the ramstage. */</span><br><span> run_ramstage();</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void car_stage_entry(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long bist = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_romstage_entry(bist);</span><br><span style="color: hsl(120, 100%, 40%);">+ platform_enter_postcar();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc</span><br><span>index bbd98da..ed132d3 100644</span><br><span>--- a/src/cpu/intel/haswell/Makefile.inc</span><br><span>+++ b/src/cpu/intel/haswell/Makefile.inc</span><br><span>@@ -16,7 +16,14 @@</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c</span><br><span> smm-y += monotonic_timer.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)</span><br><span> cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span style="color: hsl(120, 100%, 40%);">+else</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../car/non-evict/cache_as_ram_bootblock.S</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../car/bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock_gcc.c</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> postcar-y += ../car/non-evict/exit_car.S</span><br><span> </span><br><span> subdirs-y += ../../x86/tsc</span><br><span>diff --git a/src/cpu/intel/haswell/bootblock_gcc.c b/src/cpu/intel/haswell/bootblock_gcc.c</span><br><span>new file mode 100644</span><br><span>index 0000000..7baa2a8</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/haswell/bootblock_gcc.c</span><br><span>@@ -0,0 +1,79 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <halt.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/microcode/microcode.c></span><br><span style="color: hsl(120, 100%, 40%);">+#include "haswell.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/lynxpoint/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_flex_ratio_to_tdp_nominal(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t flex_ratio, msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 soft_reset;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 nominal_ratio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Check for Flex Ratio support */</span><br><span style="color: hsl(120, 100%, 40%);">+ flex_ratio = rdmsr(MSR_FLEX_RATIO);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(flex_ratio.lo & FLEX_RATIO_EN))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Check for >0 configurable TDPs */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PLATFORM_INFO);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (((msr.hi >> 1) & 3) == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Use nominal TDP ratio for flex ratio */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);</span><br><span style="color: hsl(120, 100%, 40%);">+ nominal_ratio = msr.lo & 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* See if flex ratio is already set to nominal TDP ratio */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set flex ratio to nominal TDP ratio */</span><br><span style="color: hsl(120, 100%, 40%);">+ flex_ratio.lo &= ~0xff00;</span><br><span style="color: hsl(120, 100%, 40%);">+ flex_ratio.lo |= nominal_ratio << 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ flex_ratio.lo |= FLEX_RATIO_LOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_FLEX_RATIO, flex_ratio);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set flex ratio in soft reset data register bits 11:6.</span><br><span style="color: hsl(120, 100%, 40%);">+ * RCBA region is enabled in southbridge bootblock */</span><br><span style="color: hsl(120, 100%, 40%);">+ soft_reset = RCBA32(SOFT_RESET_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+ soft_reset &= ~(0x3f << 6);</span><br><span style="color: hsl(120, 100%, 40%);">+ soft_reset |= (nominal_ratio & 0x3f) << 6;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(SOFT_RESET_DATA) = soft_reset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set soft reset control to use register value */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32_OR(SOFT_RESET_CTRL, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Issue warm reset, will be "CPU only" due to soft reset data */</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x0, 0xcf9);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x6, 0xcf9);</span><br><span style="color: hsl(120, 100%, 40%);">+ halt();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_cpu_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set flex ratio and reset if needed */</span><br><span style="color: hsl(120, 100%, 40%);">+ set_flex_ratio_to_tdp_nominal();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig</span><br><span>index 3a47195..9019a8b 100644</span><br><span>--- a/src/northbridge/intel/haswell/Kconfig</span><br><span>+++ b/src/northbridge/intel/haswell/Kconfig</span><br><span>@@ -23,6 +23,8 @@</span><br><span> select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span> select POSTCAR_STAGE</span><br><span> select POSTCAR_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select C_ENVIRONMENT_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOOTBLOCK_CONSOLE</span><br><span> </span><br><span> if NORTHBRIDGE_INTEL_HASWELL</span><br><span> </span><br><span>@@ -59,6 +61,13 @@</span><br><span> help</span><br><span> The amount of cache-as-ram region required by the reference code.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DCACHE_BSP_STACK_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The amount of anticipated stack usage in CAR by bootblock and</span><br><span style="color: hsl(120, 100%, 40%);">+ other stages.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config HAVE_MRC</span><br><span> bool "Add a System Agent binary"</span><br><span> help</span><br><span>diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>index 055c2a8..1566c73 100644</span><br><span>--- a/src/northbridge/intel/haswell/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>@@ -15,6 +15,8 @@</span><br><span> </span><br><span> ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock_gcc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ramstage-y += ram_calc.c</span><br><span> ramstage-y += northbridge.c</span><br><span> ramstage-y += gma.c</span><br><span>diff --git a/src/northbridge/intel/haswell/bootblock_gcc.c b/src/northbridge/intel/haswell/bootblock_gcc.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e907bca</span><br><span>--- /dev/null</span><br><span>+++ b/src/northbridge/intel/haswell/bootblock_gcc.c</span><br><span>@@ -0,0 +1,38 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "haswell.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_northbridge_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The "io" variant of the config access is explicitly used to</span><br><span style="color: hsl(120, 100%, 40%);">+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to</span><br><span style="color: hsl(120, 100%, 40%);">+ * to true. That way all subsequent non-explicit config accesses use</span><br><span style="color: hsl(120, 100%, 40%);">+ * MCFG. This code also assumes that bootblock_northbridge_init() is</span><br><span style="color: hsl(120, 100%, 40%);">+ * the first thing called in the non-asm boot block code. The final</span><br><span style="color: hsl(120, 100%, 40%);">+ * assumption is that no assembly code is using the</span><br><span style="color: hsl(120, 100%, 40%);">+ * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * The PCIEXBAR is assumed to live in the memory mapped IO space under</span><br><span style="color: hsl(120, 100%, 40%);">+ * 4GiB.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>index 6abdf4d..2bd66a1 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>+++ b/src/southbridge/intel/lynxpoint/Makefile.inc</span><br><span>@@ -15,6 +15,8 @@</span><br><span> </span><br><span> ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock_gcc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ramstage-y += pch.c</span><br><span> ramstage-y += azalia.c</span><br><span> ramstage-y += lpc.c</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/bootblock_gcc.c b/src/southbridge/intel/lynxpoint/bootblock_gcc.c</span><br><span>new file mode 100644</span><br><span>index 0000000..dd9e112</span><br><span>--- /dev/null</span><br><span>+++ b/src/southbridge/intel/lynxpoint/bootblock_gcc.c</span><br><span>@@ -0,0 +1,82 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "pch.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable Prefetching and Caching.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_spi_prefetch(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = PCI_DEV(0, 0x1f, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(dev, 0xdc);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 &= ~(3 << 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, 0xdc, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void map_rcba(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_port80_on_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable port 80 POST on LPC. The chipset does this by default,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but it doesn't appear to hurt anything. */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 gcs = RCBA32(GCS);</span><br><span style="color: hsl(120, 100%, 40%);">+ gcs = gcs & ~0x4;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(GCS) = gcs;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_spi_speed(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 fdod;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ssfc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Observe SPI Descriptor Component Section 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ SPIBAR32(FDOC) = 0x1000;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Extract the Write/Erase SPI Frequency from descriptor */</span><br><span style="color: hsl(120, 100%, 40%);">+ fdod = SPIBAR32(FDOD);</span><br><span style="color: hsl(120, 100%, 40%);">+ fdod >>= 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ fdod &= 7;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Software Sequence frequency to match */</span><br><span style="color: hsl(120, 100%, 40%);">+ ssfc = SPIBAR8(SSFC + 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ ssfc &= ~7;</span><br><span style="color: hsl(120, 100%, 40%);">+ ssfc |= fdod;</span><br><span style="color: hsl(120, 100%, 40%);">+ SPIBAR8(SSFC + 2) = ssfc;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_southbridge_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ map_rcba();</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_spi_prefetch();</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_port80_on_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+ set_spi_speed();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable upper 128bytes of CMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(RC) = (1 << 2);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c</span><br><span>index cb4bc7e..ae7299b 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/early_pch.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/early_pch.c</span><br><span>@@ -139,8 +139,6 @@</span><br><span> setup_pch_gpios(gpio_map);</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- console_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> pch_generic_setup();</span><br><span> </span><br><span> /* Enable SMBus for reading SPDs. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26859">change 26859</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26859"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea </div>
<div style="display:none"> Gerrit-Change-Number: 26859 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>