[coreboot-gerrit] Change in coreboot[master]: arch/arm/armv7: Fix coding style
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Mon Jun 4 14:55:45 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26831
Change subject: arch/arm/armv7: Fix coding style
......................................................................
arch/arm/armv7: Fix coding style
Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/arch/arm/armv7/bootblock.S
M src/arch/arm/armv7/cpu.S
M src/arch/arm/armv7/mmu.c
M src/arch/arm/armv7/thread.c
4 files changed, 72 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/26831/1
diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
index da7509d..e2d76a1 100644
--- a/src/arch/arm/armv7/bootblock.S
+++ b/src/arch/arm/armv7/bootblock.S
@@ -89,11 +89,11 @@
/* Set stackpointer in internal RAM to call bootblock main() */
ldr sp, =_estack
ldr r0,=0x00000000
- /*
- * The current design of cpu_info places the struct at the top of the
- * stack. Free enough space to accommodate for that, but make sure it's
- * 8-byte aligned for ABI compliance.
- */
+ /*
+ * The current design of cpu_info places the struct at the top of the
+ * stack. Free enough space to accommodate for that, but make sure it's
+ * 8-byte aligned for ABI compliance.
+ */
sub sp, sp, #16
bl main
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S
index 21a16d2..1f6cd5b 100644
--- a/src/arch/arm/armv7/cpu.S
+++ b/src/arch/arm/armv7/cpu.S
@@ -84,7 +84,7 @@
lsl ip, ip, r2 @ shift by that into way position
mov r0, #1
lsl r2, r0, r2 @ r2 now contains the way decr
- mov r0, r3 @ get sets/level (no way yet)
+ mov r0, r3 @ get sets/level (no way yet)
orr r3, r3, ip @ merge way into way/set/level
bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1
sub r2, r2, r0 @ subtract from way decr
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 957b4b6..4f1f08e 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -46,7 +46,7 @@
0ULL << 54 | /* XN. 0:Not restricted */ \
0ULL << 53 | /* PXN. 0:Not restricted */ \
1 << 10 | /* AF. 1:Accessed. This is to prevent access \
- * fault when accessed for the first time */ \
+ * fault when accessed for the first time */ \
0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \
0 << 5 | /* NS. 0:Output address is in Secure space */ \
0 << 1 | /* block/table. 0:block entry */ \
@@ -196,7 +196,7 @@
/* Make sure the range is contained within a single superpage. */
assert(((start_kb + size_kb - 1) & (BLOCK_MASK/KiB))
- == (start_kb & (BLOCK_MASK/KiB)) && start_kb < 4 * (GiB/KiB));
+ == (start_kb & (BLOCK_MASK/KiB)) && start_kb < 4 * (GiB/KiB));
if ((*pgd_entry & ~NEXTLEVEL_MASK) != ATTR_NEXTLEVEL)
table = mmu_create_subtable(pgd_entry);
@@ -219,7 +219,7 @@
start_kb * KiB, (start_kb + size_kb) * KiB, attrs[policy].name);
u32 end_kb = ALIGN_UP((start_kb + size_kb), PAGE_SIZE/KiB) -
- (start_kb & ~mask);
+ (start_kb & ~mask);
assert(end_kb <= BLOCK_SIZE/KiB);
@@ -238,7 +238,7 @@
start_kb * KiB, (start_kb + size_kb) * KiB);
mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB),
div_round_up((start_kb + size_kb) & mask, PAGE_SIZE/KiB),
- (start_kb & ~mask) * KiB, PAGE_SHIFT, 0);
+ start_kb & ~mask) * KiB, PAGE_SHIFT, 0);
}
void mmu_disable_range(u32 start_mb, u32 size_mb)
@@ -285,53 +285,53 @@
int i;
printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
- ttb_buff);
+ ttb_buff);
ASSERT((read_mmfr0() & 0xf) >= 5);
/*
- * Set MAIR
- * See B4.1.104 of ARMv7 Architecture Reference Manual
- */
+ * Set MAIR
+ * See B4.1.104 of ARMv7 Architecture Reference Manual
+ */
write_mair0(
0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered,
- * Non-Cacheable */
+ * Non-Cacheable */
0xaa << (MAIR_INDX_WT*8) | /* Write-Thru,
- * Read-Allocate */
+ * Read-Allocate */
0xff << (MAIR_INDX_WB*8) /* Write-Back,
- * Read/Write-Allocate */
+ * Read/Write-Allocate */
);
/*
- * Set up L1 table
- * Once set here, L1 table won't be modified by coreboot.
- * See B3.6.1 of ARMv7 Architecture Reference Manual
- */
+ * Set up L1 table
+ * Once set here, L1 table won't be modified by coreboot.
+ * See B3.6.1 of ARMv7 Architecture Reference Manual
+ */
for (i = 0; i < 4; i++) {
pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
- ATTR_NEXTLEVEL;
+ ATTR_NEXTLEVEL;
pmd += BLOCK_SIZE / PAGE_SIZE;
}
/*
- * Set TTBR0
- */
+ * Set TTBR0
+ */
write_ttbr0((uintptr_t)pgd_buff);
} else {
printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
/*
- * Translation table base 0 address is in bits 31:14-N, where N
- * is given by bits 2:0 in TTBCR (which we set to 0). All lower
- * bits in this register should be zero for coreboot.
- */
+ * Translation table base 0 address is in bits 31:14-N, where N
+ * is given by bits 2:0 in TTBCR (which we set to 0). All lower
+ * bits in this register should be zero for coreboot.
+ */
write_ttbr0((uintptr_t)ttb_buff);
}
/*
- * Set TTBCR
- * See B4.1.153 of ARMv7 Architecture Reference Manual
- * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected.
- */
+ * Set TTBCR
+ * See B4.1.153 of ARMv7 Architecture Reference Manual
+ * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected.
+ */
write_ttbcr(
CONFIG_ARM_LPAE << 31 | /* EAE. 1:Enable LPAE */
0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */
diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c
index 3b8d1af..e27fc41 100644
--- a/src/arch/arm/armv7/thread.c
+++ b/src/arch/arm/armv7/thread.c
@@ -39,22 +39,22 @@
}
void arch_prepare_thread(struct thread *t,
- void asmlinkage(*thread_entry)(void *), void *arg)
+ void asmlinkage(*thread_entry)(void *), void *arg)
{
uintptr_t stack = t->stack_current;
int i;
uintptr_t poison = 0xdeadbeef;
/* Push the LR. thread_entry()
- * is assumed to never return.
- */
+ * is assumed to never return.
+ */
stack = push_stack(stack, (uintptr_t)thread_entry);
/* Make room for the registers.
- * Poison the initial stack. This is good hygiene and finds bugs.
- * Poisoning the stack with different values helps when you're
- * hunting for (e.g.) misaligned stacks or other such
- * weirdness. The -1 is because we already pushed lr.
- */
+ * Poison the initial stack. This is good hygiene and finds bugs.
+ * Poisoning the stack with different values helps when you're
+ * hunting for (e.g.) misaligned stacks or other such
+ * weirdness. The -1 is because we already pushed lr.
+ */
for (i = 0; i < sizeof(struct pushed_regs) / sizeof(u32) - 1; i++)
stack = push_stack(stack, poison++);
@@ -71,38 +71,38 @@
switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack)
{
/* Defintions for those of us not totally familiar with ARM:
- * R15 -- PC, R14 -- LR, R13 -- SP
- * R0-R3 need not be saved, nor R12.
- * on entry, the only saved state is in LR -- the old PC.
- * The args are in R0,R1.
- * R0 is the new stack
- * R1 is a pointer to the old stack save location
- * Push R4-R11 and LR
- * then switch stacks
- * then pop R0-R12 and LR
- * then mov PC,LR
- *
- * stack layout
- * +------------+
- * | LR | <-- sp + 0x20
- * +------------+
- * | R11 | <-- sp + 0x1c
- * +------------+
- * | R10 | <-- sp + 0x18
- * +------------+
- * | R9 | <-- sp + 0x14
- * +------------+
- * | R8 | <-- sp + 0x10
- * +------------+
- * | R7 | <-- sp + 0x0c
- * +------------+
- * | R6 | <-- sp + 0x08
- * +------------+
- * | R5 | <-- sp + 0x04
- * +------------+
- * | R4 | <-- sp + 0x00
- * +------------+
- */
+ * R15 -- PC, R14 -- LR, R13 -- SP
+ * R0-R3 need not be saved, nor R12.
+ * on entry, the only saved state is in LR -- the old PC.
+ * The args are in R0,R1.
+ * R0 is the new stack
+ * R1 is a pointer to the old stack save location
+ * Push R4-R11 and LR
+ * then switch stacks
+ * then pop R0-R12 and LR
+ * then mov PC,LR
+ *
+ * stack layout
+ * +------------+
+ * | LR | <-- sp + 0x20
+ * +------------+
+ * | R11 | <-- sp + 0x1c
+ * +------------+
+ * | R10 | <-- sp + 0x18
+ * +------------+
+ * | R9 | <-- sp + 0x14
+ * +------------+
+ * | R8 | <-- sp + 0x10
+ * +------------+
+ * | R7 | <-- sp + 0x0c
+ * +------------+
+ * | R6 | <-- sp + 0x08
+ * +------------+
+ * | R5 | <-- sp + 0x04
+ * +------------+
+ * | R4 | <-- sp + 0x00
+ * +------------+
+ */
asm volatile (
/* save context. */
"push {r4-r11,lr}\n\t"
--
To view, visit https://review.coreboot.org/26831
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f
Gerrit-Change-Number: 26831
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180604/b586da97/attachment-0001.html>
More information about the coreboot-gerrit
mailing list