<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26831">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">arch/arm/armv7: Fix coding style<br><br>Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/arch/arm/armv7/bootblock.S<br>M src/arch/arm/armv7/cpu.S<br>M src/arch/arm/armv7/mmu.c<br>M src/arch/arm/armv7/thread.c<br>4 files changed, 72 insertions(+), 72 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/26831/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S</span><br><span>index da7509d..e2d76a1 100644</span><br><span>--- a/src/arch/arm/armv7/bootblock.S</span><br><span>+++ b/src/arch/arm/armv7/bootblock.S</span><br><span>@@ -89,11 +89,11 @@</span><br><span> /* Set stackpointer in internal RAM to call bootblock main() */</span><br><span> ldr sp, =_estack</span><br><span> ldr r0,=0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * The current design of cpu_info places the struct at the top of the</span><br><span style="color: hsl(0, 100%, 40%);">- * stack. Free enough space to accommodate for that, but make sure it's</span><br><span style="color: hsl(0, 100%, 40%);">- * 8-byte aligned for ABI compliance.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The current design of cpu_info places the struct at the top of the</span><br><span style="color: hsl(120, 100%, 40%);">+ * stack. Free enough space to accommodate for that, but make sure it's</span><br><span style="color: hsl(120, 100%, 40%);">+ * 8-byte aligned for ABI compliance.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> sub sp, sp, #16</span><br><span> bl main</span><br><span> </span><br><span>diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S</span><br><span>index 21a16d2..1f6cd5b 100644</span><br><span>--- a/src/arch/arm/armv7/cpu.S</span><br><span>+++ b/src/arch/arm/armv7/cpu.S</span><br><span>@@ -84,7 +84,7 @@</span><br><span> lsl ip, ip, r2 @ shift by that into way position</span><br><span> mov r0, #1</span><br><span> lsl r2, r0, r2 @ r2 now contains the way decr</span><br><span style="color: hsl(0, 100%, 40%);">- mov r0, r3 @ get sets/level (no way yet)</span><br><span style="color: hsl(120, 100%, 40%);">+ mov r0, r3 @ get sets/level (no way yet)</span><br><span> orr r3, r3, ip @ merge way into way/set/level</span><br><span> bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1</span><br><span> sub r2, r2, r0 @ subtract from way decr</span><br><span>diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c</span><br><span>index 957b4b6..4f1f08e 100644</span><br><span>--- a/src/arch/arm/armv7/mmu.c</span><br><span>+++ b/src/arch/arm/armv7/mmu.c</span><br><span>@@ -46,7 +46,7 @@</span><br><span> 0ULL << 54 | /* XN. 0:Not restricted */ \</span><br><span> 0ULL << 53 | /* PXN. 0:Not restricted */ \</span><br><span> 1 << 10 | /* AF. 1:Accessed. This is to prevent access \</span><br><span style="color: hsl(0, 100%, 40%);">- * fault when accessed for the first time */ \</span><br><span style="color: hsl(120, 100%, 40%);">+ * fault when accessed for the first time */ \</span><br><span> 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \</span><br><span> 0 << 5 | /* NS. 0:Output address is in Secure space */ \</span><br><span> 0 << 1 | /* block/table. 0:block entry */ \</span><br><span>@@ -196,7 +196,7 @@</span><br><span> </span><br><span> /* Make sure the range is contained within a single superpage. */</span><br><span> assert(((start_kb + size_kb - 1) & (BLOCK_MASK/KiB))</span><br><span style="color: hsl(0, 100%, 40%);">- == (start_kb & (BLOCK_MASK/KiB)) && start_kb < 4 * (GiB/KiB));</span><br><span style="color: hsl(120, 100%, 40%);">+ == (start_kb & (BLOCK_MASK/KiB)) && start_kb < 4 * (GiB/KiB));</span><br><span> </span><br><span> if ((*pgd_entry & ~NEXTLEVEL_MASK) != ATTR_NEXTLEVEL)</span><br><span> table = mmu_create_subtable(pgd_entry);</span><br><span>@@ -219,7 +219,7 @@</span><br><span> start_kb * KiB, (start_kb + size_kb) * KiB, attrs[policy].name);</span><br><span> </span><br><span> u32 end_kb = ALIGN_UP((start_kb + size_kb), PAGE_SIZE/KiB) -</span><br><span style="color: hsl(0, 100%, 40%);">- (start_kb & ~mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ (start_kb & ~mask);</span><br><span> </span><br><span> assert(end_kb <= BLOCK_SIZE/KiB);</span><br><span> </span><br><span>@@ -238,7 +238,7 @@</span><br><span> start_kb * KiB, (start_kb + size_kb) * KiB);</span><br><span> mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB),</span><br><span> div_round_up((start_kb + size_kb) & mask, PAGE_SIZE/KiB),</span><br><span style="color: hsl(0, 100%, 40%);">- (start_kb & ~mask) * KiB, PAGE_SHIFT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ start_kb & ~mask) * KiB, PAGE_SHIFT, 0);</span><br><span> }</span><br><span> </span><br><span> void mmu_disable_range(u32 start_mb, u32 size_mb)</span><br><span>@@ -285,53 +285,53 @@</span><br><span> int i;</span><br><span> </span><br><span> printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",</span><br><span style="color: hsl(0, 100%, 40%);">- ttb_buff);</span><br><span style="color: hsl(120, 100%, 40%);">+ ttb_buff);</span><br><span> ASSERT((read_mmfr0() & 0xf) >= 5);</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set MAIR</span><br><span style="color: hsl(0, 100%, 40%);">- * See B4.1.104 of ARMv7 Architecture Reference Manual</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set MAIR</span><br><span style="color: hsl(120, 100%, 40%);">+ * See B4.1.104 of ARMv7 Architecture Reference Manual</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> write_mair0(</span><br><span> 0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered,</span><br><span style="color: hsl(0, 100%, 40%);">- * Non-Cacheable */</span><br><span style="color: hsl(120, 100%, 40%);">+ * Non-Cacheable */</span><br><span> 0xaa << (MAIR_INDX_WT*8) | /* Write-Thru,</span><br><span style="color: hsl(0, 100%, 40%);">- * Read-Allocate */</span><br><span style="color: hsl(120, 100%, 40%);">+ * Read-Allocate */</span><br><span> 0xff << (MAIR_INDX_WB*8) /* Write-Back,</span><br><span style="color: hsl(0, 100%, 40%);">- * Read/Write-Allocate */</span><br><span style="color: hsl(120, 100%, 40%);">+ * Read/Write-Allocate */</span><br><span> );</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set up L1 table</span><br><span style="color: hsl(0, 100%, 40%);">- * Once set here, L1 table won't be modified by coreboot.</span><br><span style="color: hsl(0, 100%, 40%);">- * See B3.6.1 of ARMv7 Architecture Reference Manual</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set up L1 table</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once set here, L1 table won't be modified by coreboot.</span><br><span style="color: hsl(120, 100%, 40%);">+ * See B3.6.1 of ARMv7 Architecture Reference Manual</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> for (i = 0; i < 4; i++) {</span><br><span> pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |</span><br><span style="color: hsl(0, 100%, 40%);">- ATTR_NEXTLEVEL;</span><br><span style="color: hsl(120, 100%, 40%);">+ ATTR_NEXTLEVEL;</span><br><span> pmd += BLOCK_SIZE / PAGE_SIZE;</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set TTBR0</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set TTBR0</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> write_ttbr0((uintptr_t)pgd_buff);</span><br><span> } else {</span><br><span> printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Translation table base 0 address is in bits 31:14-N, where N</span><br><span style="color: hsl(0, 100%, 40%);">- * is given by bits 2:0 in TTBCR (which we set to 0). All lower</span><br><span style="color: hsl(0, 100%, 40%);">- * bits in this register should be zero for coreboot.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ * Translation table base 0 address is in bits 31:14-N, where N</span><br><span style="color: hsl(120, 100%, 40%);">+ * is given by bits 2:0 in TTBCR (which we set to 0). All lower</span><br><span style="color: hsl(120, 100%, 40%);">+ * bits in this register should be zero for coreboot.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> write_ttbr0((uintptr_t)ttb_buff);</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set TTBCR</span><br><span style="color: hsl(0, 100%, 40%);">- * See B4.1.153 of ARMv7 Architecture Reference Manual</span><br><span style="color: hsl(0, 100%, 40%);">- * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set TTBCR</span><br><span style="color: hsl(120, 100%, 40%);">+ * See B4.1.153 of ARMv7 Architecture Reference Manual</span><br><span style="color: hsl(120, 100%, 40%);">+ * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> write_ttbcr(</span><br><span> CONFIG_ARM_LPAE << 31 | /* EAE. 1:Enable LPAE */</span><br><span> 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */</span><br><span>diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c</span><br><span>index 3b8d1af..e27fc41 100644</span><br><span>--- a/src/arch/arm/armv7/thread.c</span><br><span>+++ b/src/arch/arm/armv7/thread.c</span><br><span>@@ -39,22 +39,22 @@</span><br><span> }</span><br><span> </span><br><span> void arch_prepare_thread(struct thread *t,</span><br><span style="color: hsl(0, 100%, 40%);">- void asmlinkage(*thread_entry)(void *), void *arg)</span><br><span style="color: hsl(120, 100%, 40%);">+ void asmlinkage(*thread_entry)(void *), void *arg)</span><br><span> {</span><br><span> uintptr_t stack = t->stack_current;</span><br><span> int i;</span><br><span> uintptr_t poison = 0xdeadbeef;</span><br><span> </span><br><span> /* Push the LR. thread_entry()</span><br><span style="color: hsl(0, 100%, 40%);">- * is assumed to never return.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ * is assumed to never return.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> stack = push_stack(stack, (uintptr_t)thread_entry);</span><br><span> /* Make room for the registers.</span><br><span style="color: hsl(0, 100%, 40%);">- * Poison the initial stack. This is good hygiene and finds bugs.</span><br><span style="color: hsl(0, 100%, 40%);">- * Poisoning the stack with different values helps when you're</span><br><span style="color: hsl(0, 100%, 40%);">- * hunting for (e.g.) misaligned stacks or other such</span><br><span style="color: hsl(0, 100%, 40%);">- * weirdness. The -1 is because we already pushed lr.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ * Poison the initial stack. This is good hygiene and finds bugs.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Poisoning the stack with different values helps when you're</span><br><span style="color: hsl(120, 100%, 40%);">+ * hunting for (e.g.) misaligned stacks or other such</span><br><span style="color: hsl(120, 100%, 40%);">+ * weirdness. The -1 is because we already pushed lr.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> for (i = 0; i < sizeof(struct pushed_regs) / sizeof(u32) - 1; i++)</span><br><span> stack = push_stack(stack, poison++);</span><br><span> </span><br><span>@@ -71,38 +71,38 @@</span><br><span> switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack)</span><br><span> {</span><br><span> /* Defintions for those of us not totally familiar with ARM:</span><br><span style="color: hsl(0, 100%, 40%);">- * R15 -- PC, R14 -- LR, R13 -- SP</span><br><span style="color: hsl(0, 100%, 40%);">- * R0-R3 need not be saved, nor R12.</span><br><span style="color: hsl(0, 100%, 40%);">- * on entry, the only saved state is in LR -- the old PC.</span><br><span style="color: hsl(0, 100%, 40%);">- * The args are in R0,R1.</span><br><span style="color: hsl(0, 100%, 40%);">- * R0 is the new stack</span><br><span style="color: hsl(0, 100%, 40%);">- * R1 is a pointer to the old stack save location</span><br><span style="color: hsl(0, 100%, 40%);">- * Push R4-R11 and LR</span><br><span style="color: hsl(0, 100%, 40%);">- * then switch stacks</span><br><span style="color: hsl(0, 100%, 40%);">- * then pop R0-R12 and LR</span><br><span style="color: hsl(0, 100%, 40%);">- * then mov PC,LR</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * stack layout</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- * | LR | <-- sp + 0x20</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- * | R11 | <-- sp + 0x1c</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- * | R10 | <-- sp + 0x18</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- * | R9 | <-- sp + 0x14</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- * | R8 | <-- sp + 0x10</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- * | R7 | <-- sp + 0x0c</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- * | R6 | <-- sp + 0x08</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- * | R5 | <-- sp + 0x04</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- * | R4 | <-- sp + 0x00</span><br><span style="color: hsl(0, 100%, 40%);">- * +------------+</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ * R15 -- PC, R14 -- LR, R13 -- SP</span><br><span style="color: hsl(120, 100%, 40%);">+ * R0-R3 need not be saved, nor R12.</span><br><span style="color: hsl(120, 100%, 40%);">+ * on entry, the only saved state is in LR -- the old PC.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The args are in R0,R1.</span><br><span style="color: hsl(120, 100%, 40%);">+ * R0 is the new stack</span><br><span style="color: hsl(120, 100%, 40%);">+ * R1 is a pointer to the old stack save location</span><br><span style="color: hsl(120, 100%, 40%);">+ * Push R4-R11 and LR</span><br><span style="color: hsl(120, 100%, 40%);">+ * then switch stacks</span><br><span style="color: hsl(120, 100%, 40%);">+ * then pop R0-R12 and LR</span><br><span style="color: hsl(120, 100%, 40%);">+ * then mov PC,LR</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * stack layout</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | LR | <-- sp + 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | R11 | <-- sp + 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | R10 | <-- sp + 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | R9 | <-- sp + 0x14</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | R8 | <-- sp + 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | R7 | <-- sp + 0x0c</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | R6 | <-- sp + 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | R5 | <-- sp + 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ * | R4 | <-- sp + 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ * +------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> asm volatile (</span><br><span> /* save context. */</span><br><span> "push {r4-r11,lr}\n\t"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26831">change 26831</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26831"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib5d574347373009c8021597f555e6e86c2c0c41f </div>
<div style="display:none"> Gerrit-Change-Number: 26831 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>