[coreboot-gerrit] Change in coreboot[master]: mb/iei: Get rid of whitespace before tab
Patrick Georgi (Code Review)
gerrit at coreboot.org
Mon Jun 4 11:02:41 CEST 2018
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/26625 )
Change subject: mb/iei: Get rid of whitespace before tab
......................................................................
mb/iei: Get rid of whitespace before tab
Change-Id: I750ec788b7526ee2a7aa803bffb93805cedfb2ff
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
Reviewed-on: https://review.coreboot.org/26625
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi at google.com>
---
M src/mainboard/iei/kino-780am2-fam10/devicetree.cb
M src/mainboard/iei/kino-780am2-fam10/dsdt.asl
2 files changed, 21 insertions(+), 21 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb
index 1dffb4b..6517c97 100644
--- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb
+++ b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb
@@ -9,7 +9,7 @@
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
- device pci 0.0 on end # HT 0x9600
+ device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 on end # PCIE P2P bridge 0x960b
@@ -39,7 +39,7 @@
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
- device pci 14.0 on # SM
+ device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl
index 402b520..cd158fa 100644
--- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl
+++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl
@@ -239,9 +239,9 @@
PWMK, 1,
PWNS, 1,
- /* Offset(0x61), */ /* Options_1 */
- /* ,7, */
- /* R617,1, */
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
Offset(0x65), /* UsbPMControl */
, 4,
@@ -837,7 +837,7 @@
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ * Store(0,\_SB.PWDE)
*}
*/
@@ -853,13 +853,13 @@
* used, so it could be removed.
*
*
- * \_GTS OEM Going To Sleep method
+ * \_GTS OEM Going To Sleep method
*
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
*
- * Exit:
- * -none-
+ * Exit:
+ * -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@@ -1026,7 +1026,7 @@
/* PCIe HotPlug event */
/* Method(_L0F) {
- * DBGO("\\_GPE\\_L0F\n")
+ * DBGO("\\_GPE\\_L0F\n")
* }
*/
@@ -1049,19 +1049,19 @@
/* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) {
- * DBGO("\\_GPE\\_L13\n")
+ * DBGO("\\_GPE\\_L13\n")
* }
*/
/* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) {
- * DBGO("\\_GPE\\_L14\n")
+ * DBGO("\\_GPE\\_L14\n")
* }
*/
/* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) {
- * DBGO("\\_GPE\\_L15\n")
+ * DBGO("\\_GPE\\_L15\n")
* }
*/
@@ -1073,7 +1073,7 @@
/* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) {
- * DBGO("\\_GPE\\_L17\n")
+ * DBGO("\\_GPE\\_L17\n")
* }
*/
@@ -1090,7 +1090,7 @@
/* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) {
- * DBGO("\\_GPE\\_L19\n")
+ * DBGO("\\_GPE\\_L19\n")
* }
*/
@@ -1121,7 +1121,7 @@
/* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) {
- * DBGO("\\_GPE\\_L1E\n")
+ * DBGO("\\_GPE\\_L1E\n")
* }
*/
@@ -1131,7 +1131,7 @@
* }
*/
- } /* End Scope GPE */
+ } /* End Scope GPE */
#include "acpi/usb.asl"
@@ -1520,7 +1520,7 @@
0xF300 /* length */
)
- Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
#if 0
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
@@ -1652,7 +1652,7 @@
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
- * Store(0,\PWDE)
+ * Store(0,\PWDE)
* }
*/
} /* End Method(_SB._INI) */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I750ec788b7526ee2a7aa803bffb93805cedfb2ff
Gerrit-Change-Number: 26625
Gerrit-PatchSet: 2
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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