[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Make use of SkipMpInit for MP Init
Subrata Banik (Code Review)
gerrit at coreboot.org
Mon Jun 4 07:01:58 CEST 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26818
Change subject: soc/intel/skylake: Make use of SkipMpInit for MP Init
......................................................................
soc/intel/skylake: Make use of SkipMpInit for MP Init
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/mainboard/google/chell/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/lars/devicetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
21 files changed, 8 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/26818/1
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 2f07753..fa1fde4 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -48,7 +48,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index b42acbb..fa12d8b 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -44,7 +44,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 45b2736..6418c7d 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -79,7 +79,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 94d9e53..19c9beb 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -48,7 +48,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 344d4b7..c860569 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -36,7 +36,6 @@
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"
- register "FspSkipMpInit" = "1"
register "PmTimerDisabled" = "1"
register "pirqa_routing" = "PCH_IRQ11"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 8ae9b05..64e7113 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -51,7 +51,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index eb45dbd..8ea5c2d 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -51,7 +51,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 5e2575f..0c4a8e8 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -50,7 +50,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 2c004c5..7cf764e 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -51,7 +51,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 91e8b46..78edcc9 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -51,7 +51,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 8e6f952..af96288 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -51,7 +51,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
index a8e835e..8751255 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
@@ -131,8 +131,6 @@
.voltage_limit = 0x5F0 \
}"
- register "FspSkipMpInit" = "1"
-
# Enable Root ports.
# PCIE Port 1 x4 -> SLOT1
register "PcieRpEnable[0]" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
index 5c41f22..f07d381 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb
@@ -132,8 +132,6 @@
.voltage_limit = 0x0 \
}"
- register "FspSkipMpInit" = "1"
-
# Enable Root ports.
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
index 2a2d761..0057a28 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb
@@ -128,8 +128,6 @@
.voltage_limit = 0x0 \
}"
- register "FspSkipMpInit" = "1"
-
# Enable Root port.
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index aec57b1..44aa325 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -141,8 +141,6 @@
.voltage_limit = 0x5F0 \
}"
- register "FspSkipMpInit" = "1"
-
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[4]" = "1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 6da73dc..3d3b65a 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -142,8 +142,6 @@
.voltage_limit = 0x5F0 \
}"
- register "FspSkipMpInit" = "0"
-
# Enable x1 slot
register "PcieRpEnable[7]" = "1"
register "PcieRpClkReqSupport[7]" = "1"
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index 1351741..5f61d34 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -62,7 +62,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
index 021f08a..520736c 100644
--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
@@ -62,7 +62,6 @@
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "FspSkipMpInit" = "1"
register "SaGv" = "3"
register "SerialIrqConfigSirqEnable" = "1"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 1e3fdc6..9fe19d8 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -171,7 +171,7 @@
params->SerialIrqConfigStartFramePulse =
config->SerialIrqConfigStartFramePulse;
- params->SkipMpInit = config->FspSkipMpInit;
+ params->SkipMpInit = !config->use_fsp_mp_init;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 2523554..8b98662 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -434,7 +434,12 @@
SERIAL_IRQ_FRAME_PULSE_8CLK = 2,
} SerialIrqConfigStartFramePulse;
- u8 FspSkipMpInit;
+ /*
+ * Option for mainboard to skip coreboot MP initialization
+ * 0 = Make use of coreboot MP Init
+ * 1 = Make use of FSP MP Init
+ */
+ u8 use_fsp_mp_init;
/*
* VrConfig Settings for 5 domains
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index bc78586..32b597b 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -260,7 +260,7 @@
params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
params->PchSirqMode = config->SerialIrqConfigSirqMode;
- params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit;
+ params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
--
To view, visit https://review.coreboot.org/26818
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Gerrit-Change-Number: 26818
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180604/4bbd0573/attachment-0001.html>
More information about the coreboot-gerrit
mailing list