<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26818">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Make use of SkipMpInit for MP Init<br><br>This patch provides option for mainboard to skip coreboot MP<br>initialization if required based on use_fsp_mp_init.<br><br>Option for mainboard to skip coreboot MP initialization<br>* 0 = Make use of coreboot MP Init<br>* 1 = Make use of FSP MP Init<br><br>Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/mainboard/google/chell/devicetree.cb<br>M src/mainboard/google/eve/devicetree.cb<br>M src/mainboard/google/fizz/devicetree.cb<br>M src/mainboard/google/glados/devicetree.cb<br>M src/mainboard/google/lars/devicetree.cb<br>M src/mainboard/google/poppy/variants/atlas/devicetree.cb<br>M src/mainboard/google/poppy/variants/baseboard/devicetree.cb<br>M src/mainboard/google/poppy/variants/nami/devicetree.cb<br>M src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>M src/mainboard/google/poppy/variants/nocturne/devicetree.cb<br>M src/mainboard/google/poppy/variants/soraka/devicetree.cb<br>M src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb<br>M src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb<br>M src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb<br>M src/mainboard/intel/kunimitsu/devicetree.cb<br>M src/mainboard/intel/saddlebrook/devicetree.cb<br>M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb<br>M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb<br>M src/soc/intel/skylake/chip.c<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>21 files changed, 8 insertions(+), 26 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/26818/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb</span><br><span>index 2f07753..fa1fde4 100644</span><br><span>--- a/src/mainboard/google/chell/devicetree.cb</span><br><span>+++ b/src/mainboard/google/chell/devicetree.cb</span><br><span>@@ -48,7 +48,6 @@</span><br><span>   register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb</span><br><span>index b42acbb..fa12d8b 100644</span><br><span>--- a/src/mainboard/google/eve/devicetree.cb</span><br><span>+++ b/src/mainboard/google/eve/devicetree.cb</span><br><span>@@ -44,7 +44,6 @@</span><br><span>   register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb</span><br><span>index 45b2736..6418c7d 100644</span><br><span>--- a/src/mainboard/google/fizz/devicetree.cb</span><br><span>+++ b/src/mainboard/google/fizz/devicetree.cb</span><br><span>@@ -79,7 +79,6 @@</span><br><span>       register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb</span><br><span>index 94d9e53..19c9beb 100644</span><br><span>--- a/src/mainboard/google/glados/devicetree.cb</span><br><span>+++ b/src/mainboard/google/glados/devicetree.cb</span><br><span>@@ -48,7 +48,6 @@</span><br><span>       register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb</span><br><span>index 344d4b7..c860569 100644</span><br><span>--- a/src/mainboard/google/lars/devicetree.cb</span><br><span>+++ b/src/mainboard/google/lars/devicetree.cb</span><br><span>@@ -36,7 +36,6 @@</span><br><span>       register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span>     register "SaGv" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">-       register "FspSkipMpInit" = "1"</span><br><span>   register "PmTimerDisabled" = "1"</span><br><span> </span><br><span>     register "pirqa_routing" = "PCH_IRQ11"</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>index 8ae9b05..64e7113 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>@@ -51,7 +51,6 @@</span><br><span>      register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb</span><br><span>index eb45dbd..8ea5c2d 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb</span><br><span>@@ -51,7 +51,6 @@</span><br><span>       register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb</span><br><span>index 5e2575f..0c4a8e8 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb</span><br><span>@@ -50,7 +50,6 @@</span><br><span>   register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>index 2c004c5..7cf764e 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>@@ -51,7 +51,6 @@</span><br><span>   register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>index 91e8b46..78edcc9 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>@@ -51,7 +51,6 @@</span><br><span>   register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb</span><br><span>index 8e6f952..af96288 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb</span><br><span>@@ -51,7 +51,6 @@</span><br><span>   register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb</span><br><span>index a8e835e..8751255 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb</span><br><span>@@ -131,8 +131,6 @@</span><br><span>                 .voltage_limit = 0x5F0 \</span><br><span>     }"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>   # Enable Root ports.</span><br><span>         # PCIE Port 1 x4 -> SLOT1</span><br><span>         register "PcieRpEnable[0]" = "1"</span><br><span>diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb</span><br><span>index 5c41f22..f07d381 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb</span><br><span>@@ -132,8 +132,6 @@</span><br><span>              .voltage_limit = 0x0 \</span><br><span>       }"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>   # Enable Root ports.</span><br><span>         register "PcieRpEnable[2]" = "1"</span><br><span>         register "PcieRpEnable[3]" = "1"</span><br><span>diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb</span><br><span>index 2a2d761..0057a28 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb</span><br><span>@@ -128,8 +128,6 @@</span><br><span>              .voltage_limit = 0x0 \</span><br><span>       }"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>   # Enable Root port.</span><br><span>  register "PcieRpEnable[3]" = "1"</span><br><span>         register "PcieRpEnable[4]" = "1"</span><br><span>diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb</span><br><span>index aec57b1..44aa325 100644</span><br><span>--- a/src/mainboard/intel/kunimitsu/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/kunimitsu/devicetree.cb</span><br><span>@@ -141,8 +141,6 @@</span><br><span>          .voltage_limit = 0x5F0 \</span><br><span>     }"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>   # Enable Root port 1 and 5.</span><br><span>  register "PcieRpEnable[0]" = "1"</span><br><span>         register "PcieRpEnable[4]" = "1"</span><br><span>diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb</span><br><span>index 6da73dc..3d3b65a 100644</span><br><span>--- a/src/mainboard/intel/saddlebrook/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/saddlebrook/devicetree.cb</span><br><span>@@ -142,8 +142,6 @@</span><br><span>          .voltage_limit = 0x5F0 \</span><br><span>     }"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-     register "FspSkipMpInit" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>   # Enable x1 slot</span><br><span>     register "PcieRpEnable[7]" = "1"</span><br><span>         register "PcieRpClkReqSupport[7]" = "1"</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>index 1351741..5f61d34 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>@@ -62,7 +62,6 @@</span><br><span>     register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>index 021f08a..520736c 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>@@ -62,7 +62,6 @@</span><br><span>       register "SkipExtGfxScan" = "1"</span><br><span>  register "Device4Enable" = "1"</span><br><span>   register "HeciEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "FspSkipMpInit" = "1"</span><br><span>   register "SaGv" = "3"</span><br><span>    register "SerialIrqConfigSirqEnable" = "1"</span><br><span>       register "PmConfigSlpS3MinAssert" = "2"        # 50ms</span><br><span>diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c</span><br><span>index 1e3fdc6..9fe19d8 100644</span><br><span>--- a/src/soc/intel/skylake/chip.c</span><br><span>+++ b/src/soc/intel/skylake/chip.c</span><br><span>@@ -171,7 +171,7 @@</span><br><span>         params->SerialIrqConfigStartFramePulse =</span><br><span>          config->SerialIrqConfigStartFramePulse;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  params->SkipMpInit = config->FspSkipMpInit;</span><br><span style="color: hsl(120, 100%, 40%);">+     params->SkipMpInit = !config->use_fsp_mp_init;</span><br><span> </span><br><span>     for (i = 0; i < ARRAY_SIZE(config->i2c); i++)</span><br><span>          params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];</span><br><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index 2523554..8b98662 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -434,7 +434,12 @@</span><br><span>            SERIAL_IRQ_FRAME_PULSE_8CLK = 2,</span><br><span>     } SerialIrqConfigStartFramePulse;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-   u8 FspSkipMpInit;</span><br><span style="color: hsl(120, 100%, 40%);">+     /*</span><br><span style="color: hsl(120, 100%, 40%);">+     * Option for mainboard to skip coreboot MP initialization</span><br><span style="color: hsl(120, 100%, 40%);">+     * 0 = Make use of coreboot MP Init</span><br><span style="color: hsl(120, 100%, 40%);">+    * 1 = Make use of FSP MP Init</span><br><span style="color: hsl(120, 100%, 40%);">+         */</span><br><span style="color: hsl(120, 100%, 40%);">+   u8 use_fsp_mp_init;</span><br><span> </span><br><span>      /*</span><br><span>    * VrConfig Settings for 5 domains</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index bc78586..32b597b 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -260,7 +260,7 @@</span><br><span>        params->PchSirqEnable = config->SerialIrqConfigSirqEnable;</span><br><span>     params->PchSirqMode = config->SerialIrqConfigSirqMode;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit;</span><br><span style="color: hsl(120, 100%, 40%);">+      params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init;</span><br><span> </span><br><span>      for (i = 0; i < ARRAY_SIZE(config->i2c); i++)</span><br><span>          params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26818">change 26818</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26818"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27 </div>
<div style="display:none"> Gerrit-Change-Number: 26818 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>