[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Improve D0F0_DEVEN programming

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26798


Change subject: nb/intel/x4x: Improve D0F0_DEVEN programming
......................................................................

nb/intel/x4x: Improve D0F0_DEVEN programming

According to "Intel 4 Series Chipset Family" enabling or disabling the
EP functions are only meaningful if CAPID[56] and CAPID[57] are both
0. Only set those DEVEN bits when the MCH is capable of it.

Warn if devices are not present in the devicetree.

Add all possible EP functions to the Intel DG43GT devicetree. This
might fix this board not booting with a valid ME (but probably not).

Untested.

Change-Id: I007927e19a8ea716ba6c188a92144325a077c21d
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/intel/dg43gt/devicetree.cb
M src/northbridge/intel/x4x/northbridge.c
2 files changed, 12 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/26798/1

diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb
index 70ba6bc..d277b37 100644
--- a/src/mainboard/intel/dg43gt/devicetree.cb
+++ b/src/mainboard/intel/dg43gt/devicetree.cb
@@ -30,6 +30,8 @@
 		device pci 2.1 on end			# Integrated graphics controller 2
 		device pci 3.0 off end		# ME
 		device pci 3.1 off end		# ME
+		device pci 3.2 off end		# ME
+		device pci 3.3 off end		# ME
 		chip southbridge/intel/i82801jx	# Southbridge
 			register "gpe0_en" = "0x40"
 
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 3e50229..adfc1fd 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -193,6 +193,8 @@
 	int dev, fn, bit_base;
 
 	struct device *const d0f0 = dev_find_slot(0, 0);
+	int me_capable = !((pci_read_config32(d0f0, D0F0_CAPID0 + 4)
+					>> (56 - 32)) & 3);
 
 	/* Hide internal functions based on devicetree info. */
 	for (dev = 6; dev > 0; --dev) {
@@ -202,7 +204,7 @@
 			bit_base = 13;
 			break;
 		case 3: /* ME */
-			fn = 3;
+			fn = me_capable ? 3 : -1;
 			bit_base = 6;
 			break;
 		case 2: /* IGD */
@@ -220,8 +222,14 @@
 		for (; fn >= 0; --fn) {
 			const struct device *const d =
 				dev_find_slot(0, PCI_DEVFN(dev, fn));
-			if (!d || d->enabled)
+			if (!d) {
+				printk(BIOS_WARNING,
+					"%s not found in the devicetree!\n",
+					dev_path(dev));
 				continue;
+			} else if (!d->enabled) {
+				continue;
+			}
 			const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);
 			pci_write_config32(d0f0, D0F0_DEVEN,
 					   deven & ~(1 << (bit_base + fn)));

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I007927e19a8ea716ba6c188a92144325a077c21d
Gerrit-Change-Number: 26798
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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