<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26798">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Improve D0F0_DEVEN programming<br><br>According to "Intel 4 Series Chipset Family" enabling or disabling the<br>EP functions are only meaningful if CAPID[56] and CAPID[57] are both<br>0. Only set those DEVEN bits when the MCH is capable of it.<br><br>Warn if devices are not present in the devicetree.<br><br>Add all possible EP functions to the Intel DG43GT devicetree. This<br>might fix this board not booting with a valid ME (but probably not).<br><br>Untested.<br><br>Change-Id: I007927e19a8ea716ba6c188a92144325a077c21d<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/intel/dg43gt/devicetree.cb<br>M src/northbridge/intel/x4x/northbridge.c<br>2 files changed, 12 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/26798/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb</span><br><span>index 70ba6bc..d277b37 100644</span><br><span>--- a/src/mainboard/intel/dg43gt/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/dg43gt/devicetree.cb</span><br><span>@@ -30,6 +30,8 @@</span><br><span> device pci 2.1 on end # Integrated graphics controller 2</span><br><span> device pci 3.0 off end # ME</span><br><span> device pci 3.1 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.2 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.3 off end # ME</span><br><span> chip southbridge/intel/i82801jx # Southbridge</span><br><span> register "gpe0_en" = "0x40"</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c</span><br><span>index 3e50229..adfc1fd 100644</span><br><span>--- a/src/northbridge/intel/x4x/northbridge.c</span><br><span>+++ b/src/northbridge/intel/x4x/northbridge.c</span><br><span>@@ -193,6 +193,8 @@</span><br><span> int dev, fn, bit_base;</span><br><span> </span><br><span> struct device *const d0f0 = dev_find_slot(0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ int me_capable = !((pci_read_config32(d0f0, D0F0_CAPID0 + 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> (56 - 32)) & 3);</span><br><span> </span><br><span> /* Hide internal functions based on devicetree info. */</span><br><span> for (dev = 6; dev > 0; --dev) {</span><br><span>@@ -202,7 +204,7 @@</span><br><span> bit_base = 13;</span><br><span> break;</span><br><span> case 3: /* ME */</span><br><span style="color: hsl(0, 100%, 40%);">- fn = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ fn = me_capable ? 3 : -1;</span><br><span> bit_base = 6;</span><br><span> break;</span><br><span> case 2: /* IGD */</span><br><span>@@ -220,8 +222,14 @@</span><br><span> for (; fn >= 0; --fn) {</span><br><span> const struct device *const d =</span><br><span> dev_find_slot(0, PCI_DEVFN(dev, fn));</span><br><span style="color: hsl(0, 100%, 40%);">- if (!d || d->enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!d) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_WARNING,</span><br><span style="color: hsl(120, 100%, 40%);">+ "%s not found in the devicetree!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dev_path(dev));</span><br><span> continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (!d->enabled) {</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN);</span><br><span> pci_write_config32(d0f0, D0F0_DEVEN,</span><br><span> deven & ~(1 << (bit_base + fn)));</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26798">change 26798</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26798"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I007927e19a8ea716ba6c188a92144325a077c21d </div>
<div style="display:none"> Gerrit-Change-Number: 26798 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>