[coreboot-gerrit] Change in coreboot[master]: cpu/intel/car/core2: Improve a few things

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/26784

to look at the new patch set (#2).

Change subject: cpu/intel/car/core2: Improve a few things
......................................................................

cpu/intel/car/core2: Improve a few things

This changes the following:
- compute amount variable MTRR's during runtime
- Wait for all CPU's to be in Wait for SIPI state after sending init
  INIT IPI to all AP's
- compute the PHYSMASK high during runtime and preload it to the
  MTRR_PHYS_MASK msr's
- cache the whole rom size instead of XIP_ROM_SIZE

Change-Id: I8d8672f8b577c2e7cef6e80978c4464a771f430c
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/car/core2/cache_as_ram.S
1 file changed, 82 insertions(+), 34 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/26784/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I8d8672f8b577c2e7cef6e80978c4464a771f430c
Gerrit-Change-Number: 26784
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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