<p>Arthur Heymans <strong>uploaded patch set #2</strong> to this change.</p><p><a href="https://review.coreboot.org/26784">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/car/core2: Improve a few things<br><br>This changes the following:<br>- compute amount variable MTRR's during runtime<br>- Wait for all CPU's to be in Wait for SIPI state after sending init<br>  INIT IPI to all AP's<br>- compute the PHYSMASK high during runtime and preload it to the<br>  MTRR_PHYS_MASK msr's<br>- cache the whole rom size instead of XIP_ROM_SIZE<br><br>Change-Id: I8d8672f8b577c2e7cef6e80978c4464a771f430c<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/car/core2/cache_as_ram.S<br>1 file changed, 82 insertions(+), 34 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/26784/2</pre><p>To view, visit <a href="https://review.coreboot.org/26784">change 26784</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26784"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I8d8672f8b577c2e7cef6e80978c4464a771f430c </div>
<div style="display:none"> Gerrit-Change-Number: 26784 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>