[coreboot-gerrit] Change in coreboot[master]: nb/intel/i945: Switch to POSTCAR_STAGE

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26785


Change subject: nb/intel/i945: Switch to POSTCAR_STAGE
......................................................................

nb/intel/i945: Switch to POSTCAR_STAGE

Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/socket_441/Makefile.inc
M src/cpu/intel/socket_mFCPGA478/Makefile.inc
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/i945/Makefile.inc
M src/northbridge/intel/i945/ram_calc.c
5 files changed, 12 insertions(+), 15 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/26785/1

diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc
index 7c37019..7993294 100644
--- a/src/cpu/intel/socket_441/Makefile.inc
+++ b/src/cpu/intel/socket_441/Makefile.inc
@@ -8,10 +8,7 @@
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-ifneq ($(CONFIG_POSTCAR_STAGE),y)
-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-else
 cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
 postcar-y += ../car/p4-netburst/exit_car.S
-endif
+
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
index fb5902c..139b1bb 100644
--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc
+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
@@ -11,11 +11,7 @@
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-ifneq ($(CONFIG_POSTCAR_STAGE),y)
-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
-else
 cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
 postcar-y += ../car/p4-netburst/exit_car.S
-endif
 
 romstage-y += ../car/romstage.c
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 482f98a..e04d0c3 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -28,6 +28,8 @@
 	select RELOCATABLE_RAMSTAGE
 	select INTEL_EDID
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE
 
 config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 	def_bool n
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 0e4fcfc..ffeabdc 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -29,4 +29,6 @@
 
 smm-y += udelay.c
 
+postcar-y += ram_calc.c
+
 endif
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 076744f..cde545f 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -80,9 +80,10 @@
 
 #define ROMSTAGE_RAM_STACK_SIZE 0x5000
 
-/* setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mtrrs(void)
+/* platform_enter_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use,
+ * and continues execution in postcar stage. */
+void platform_enter_postcar(void)
 {
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
@@ -106,8 +107,7 @@
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 
-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
+	run_postcar_phase(&pcf);
+
+	/* We do not return here. */
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac
Gerrit-Change-Number: 26785
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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