<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26785">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/i945: Switch to POSTCAR_STAGE<br><br>Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/socket_441/Makefile.inc<br>M src/cpu/intel/socket_mFCPGA478/Makefile.inc<br>M src/northbridge/intel/i945/Kconfig<br>M src/northbridge/intel/i945/Makefile.inc<br>M src/northbridge/intel/i945/ram_calc.c<br>5 files changed, 12 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/26785/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc</span><br><span>index 7c37019..7993294 100644</span><br><span>--- a/src/cpu/intel/socket_441/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_441/Makefile.inc</span><br><span>@@ -8,10 +8,7 @@</span><br><span> subdirs-y += ../hyperthreading</span><br><span> subdirs-y += ../speedstep</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ifneq ($(CONFIG_POSTCAR_STAGE),y)</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc</span><br><span style="color: hsl(0, 100%, 40%);">-else</span><br><span> cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S</span><br><span> postcar-y += ../car/p4-netburst/exit_car.S</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc</span><br><span>index fb5902c..139b1bb 100644</span><br><span>--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc</span><br><span>@@ -11,11 +11,7 @@</span><br><span> subdirs-y += ../hyperthreading</span><br><span> subdirs-y += ../speedstep</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ifneq ($(CONFIG_POSTCAR_STAGE),y)</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span style="color: hsl(0, 100%, 40%);">-else</span><br><span> cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S</span><br><span> postcar-y += ../car/p4-netburst/exit_car.S</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span> </span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig</span><br><span>index 482f98a..e04d0c3 100644</span><br><span>--- a/src/northbridge/intel/i945/Kconfig</span><br><span>+++ b/src/northbridge/intel/i945/Kconfig</span><br><span>@@ -28,6 +28,8 @@</span><br><span>  select RELOCATABLE_RAMSTAGE</span><br><span>  select INTEL_EDID</span><br><span>    select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+      select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+  select POSTCAR_CONSOLE</span><br><span> </span><br><span> config NORTHBRIDGE_INTEL_SUBTYPE_I945GC</span><br><span>        def_bool n</span><br><span>diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc</span><br><span>index 0e4fcfc..ffeabdc 100644</span><br><span>--- a/src/northbridge/intel/i945/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/i945/Makefile.inc</span><br><span>@@ -29,4 +29,6 @@</span><br><span> </span><br><span> smm-y += udelay.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c</span><br><span>index 076744f..cde545f 100644</span><br><span>--- a/src/northbridge/intel/i945/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/i945/ram_calc.c</span><br><span>@@ -80,9 +80,10 @@</span><br><span> </span><br><span> #define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* setup_stack_and_mtrrs() determines the stack to use after</span><br><span style="color: hsl(0, 100%, 40%);">- * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span style="color: hsl(0, 100%, 40%);">-void *setup_stack_and_mtrrs(void)</span><br><span style="color: hsl(120, 100%, 40%);">+/* platform_enter_postcar() determines the stack to use after</span><br><span style="color: hsl(120, 100%, 40%);">+ * cache-as-ram is torn down as well as the MTRR settings to use,</span><br><span style="color: hsl(120, 100%, 40%);">+ * and continues execution in postcar stage. */</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_enter_postcar(void)</span><br><span> {</span><br><span>         struct postcar_frame pcf;</span><br><span>    uintptr_t top_of_ram;</span><br><span>@@ -106,8 +107,7 @@</span><br><span>  postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span>       postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">-  * pointing to the number of MTRRs.</span><br><span style="color: hsl(0, 100%, 40%);">-      */</span><br><span style="color: hsl(0, 100%, 40%);">-     return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+        run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+        /* We do not return here. */</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26785">change 26785</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26785"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac </div>
<div style="display:none"> Gerrit-Change-Number: 26785 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>