[coreboot-gerrit] Change in coreboot[master]: mainboard/google/kahlee: Remove unused baseboard code
Martin Roth (Code Review)
gerrit at coreboot.org
Sun Jun 3 05:48:41 CEST 2018
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/26778
Change subject: mainboard/google/kahlee: Remove unused baseboard code
......................................................................
mainboard/google/kahlee: Remove unused baseboard code
This code is no longer needed.
BUG=b:107537694
TEST=Build & boot on grunt
Change-Id: I71ad01f0d4c69a618d564e514ed99550b72a6b44
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
2 files changed, 4 insertions(+), 329 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/26778/1
diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
index 6ed516f..648329f 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
@@ -129,98 +129,6 @@
.DdiLinkList = (void *)DdiList
};
-/*
- * TODO: Remove after we're done with Grunt Proto
- */
-static const PCIe_PORT_DESCRIPTOR PortListNoBayhub[] = {
- /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER_V2(
- PortDisabled, /* mPortPresent */
- ChannelTypeExt6db, /* mChannelType */
- 2, /* mDevAddress */
- 1, /* mDevFunction */
- HotplugDisabled, /* mHotplug */
- PcieGenMaxSupported, /* mMaxLinkSpeed */
- PcieGenMaxSupported, /* mMaxLinkCap */
- AspmL0sL1, /* mAspm */
- 0, /* mResetId */
- 0) /* mClkPmSupport */
- },
- /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
- PCIE_PORT_DATA_INITIALIZER_V2(
- PortEnabled, /* mPortPresent */
- ChannelTypeExt6db, /* mChannelType */
- 2, /* mDevAddress */
- 2, /* mDevFunction */
- HotplugDisabled, /* mHotplug */
- PcieGenMaxSupported, /* mMaxLinkSpeed */
- PcieGenMaxSupported, /* mMaxLinkCap */
- AspmL0sL1, /* mAspm */
- PCIE_0_RST, /* mResetId */
- 0) /* mClkPmSupport */
- },
- /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
- PCIE_PORT_DATA_INITIALIZER_V2(
- PortDisabled, /* mPortPresent */
- ChannelTypeExt6db, /* mChannelType */
- 2, /* mDevAddress */
- 3, /* mDevFunction */
- HotplugDisabled, /* mHotplug */
- PcieGenMaxSupported, /* mMaxLinkSpeed */
- PcieGenMaxSupported, /* mMaxLinkCap */
- AspmL0sL1, /* mAspm */
- PCIE_1_RST, /* mResetId */
- 0) /* mClkPmSupport */
- },
- /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),
- PCIE_PORT_DATA_INITIALIZER_V2(
- PortDisabled, /* mPortPresent */
- ChannelTypeExt6db, /* mChannelType */
- 2, /* mDevAddress */
- 4, /* mDevFunction */
- HotplugDisabled, /* mHotplug */
- PcieGenMaxSupported, /* mMaxLinkSpeed */
- PcieGenMaxSupported, /* mMaxLinkCap */
- AspmL0sL1, /* mAspm */
- PCIE_2_RST, /* mResetId */
- 0) /* mClkPmSupport */
- },
- /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */
- {
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),
- PCIE_PORT_DATA_INITIALIZER_V2(
- PortDisabled, /* mPortPresent */
- ChannelTypeExt6db, /* mChannelType */
- 2, /* mDevAddress */
- 5, /* mDevFunction */
- HotplugDisabled, /* mHotplug */
- PcieGenMaxSupported, /* mMaxLinkSpeed */
- PcieGenMaxSupported, /* mMaxLinkCap */
- AspmL0sL1, /* mAspm */
- PCIE_3_RST, /* mResetId */
- 0) /* mClkPmSupport */
- },
-};
-static const PCIe_COMPLEX_DESCRIPTOR PcieNoBayhub = {
- .Flags = DESCRIPTOR_TERMINATE_LIST,
- .SocketId = 0,
- .PciePortList = (void *)PortListNoBayhub,
- .DdiLinkList = (void *)DdiList
-};
-
/*---------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
@@ -243,9 +151,4 @@
InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
- /* Completely disable Bayhub EMMC bridge on Proto with board_id 0 */
- /* Todo: Remove when we're done with Proto */
- if (board_id() == 0)
- InitEarly->GnbConfig.PcieComplexList = (void *)&PcieNoBayhub;
-
}
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index c7bd6a5..e5dff77 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -27,60 +27,6 @@
* bootblock while GPIO pins used only by the OS should be initialized at
* ramstage.
*/
-static const struct soc_amd_gpio gpio_set_stage_reset_old[] = {
- /* GPIO_4 - EN_PP3300_WLAN */
- PAD_GPO(GPIO_4, HIGH),
-
- /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */
- PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW),
-
- /* GPIO_9 - H1_PCH_INT_ODL, SCI */
- PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS),
- PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW),
-
- /* GPIO_15 - EC_IN_RW_OD */
- PAD_GPI(GPIO_15, PULL_UP),
-
- /* GPIO_22 - EC_SCI_ODL, SCI */
- PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),
-
- /* GPIO_26 - APU_PCIE_RST_L */
- PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
-
- /* GPIO_40 - EMMC_BRIDGE_RST_L - Currently unused */
- PAD_GPI(GPIO_40, PULL_UP),
-
- /* GPIO_70 - WLAN_PE_RST_L */
- PAD_GPO(GPIO_70, HIGH),
-
- /* GPIO_74 - LPC_CLK0_EC_R */
- PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN),
-
- /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */
- PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
-
- /* GPIO_122 - APU_BIOS_FLASH_WP_L */
- PAD_GPI(GPIO_122, PULL_NONE),
-
- /* GPIO_131 - CONFIG_STRAP3 */
- PAD_GPI(GPIO_131, PULL_NONE),
-
- /* GPIO_132 - CONFIG_STRAP4 */
- PAD_GPI(GPIO_132, PULL_NONE),
-
- /* GPIO_136 - UART_PCH_RX_DEBUG_TX */
- PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
-
- /* GPIO_138 - UART_PCH_TX_DEBUG_RX */
- PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
-
- /* GPIO_139 - CONFIG_STRAP1 */
- PAD_GPI(GPIO_139, PULL_NONE),
-
- /* GPIO_142 - CONFIG_STRAP2 */
- PAD_GPI(GPIO_142, PULL_NONE),
-};
-
static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_4 - EN_PP3300_WLAN */
PAD_GPO(GPIO_4, HIGH),
@@ -138,170 +84,6 @@
PAD_GPI(GPIO_142, PULL_NONE),
};
-static const struct soc_amd_gpio gpio_set_stage_ram_old[] = {
- /* GPIO_0 - EC_PCH_PWR_BTN_ODL */
- PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),
-
- /* GPIO_1 - SYS_RST_ODL */
- PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP),
-
- /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */
- PAD_NF(GPIO_2, WAKE_L, PULL_UP),
-
- /* GPIO_3 - MEM_VOLT_SEL */
- PAD_GPI(GPIO_3, PULL_UP),
-
- /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */
- PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW),
-
- /* GPIO_7 - APU_PWROK_OD (currently not used) */
- PAD_GPI(GPIO_7, PULL_UP),
-
- /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */
- PAD_GPI(GPIO_8, PULL_UP),
-
- /* GPIO_10 - SLP_S0_L (currently not used) */
- PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),
-
- /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */
- PAD_SCI(GPIO_11, PULL_UP, EDGE_LOW),
-
- /* GPIO_12 - Unused (TP126) */
- PAD_GPI(GPIO_12, PULL_UP),
-
- /* GPIO_13 - APU_PEN_PDCT_ODL (currently not used) */
- PAD_GPI(GPIO_13, PULL_UP),
-
- /* GPIO_14 - APU_HP_INT_ODL, SCI */
- PAD_SCI(GPIO_14, PULL_UP, EDGE_LOW),
-
- /* GPIO_16 - USB_C0_OC_L */
- PAD_NF(GPIO_16, USB_OC0_L, PULL_UP),
-
- /* GPIO_17 - USB_C1_OC_L */
- PAD_NF(GPIO_17, USB_OC1_L, PULL_UP),
-
- /* GPIO_18 - USB_A0_OC_ODL */
- PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
-
- /* GPIO_19 - APU_I2C_SCL3 (Touchscreen) */
- PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
-
- /* GPIO_20 - APU_I2C_SDA3 (Touchscreen) */
- PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
-
- /* GPIO_21 - APU_PEN_INT_ODL, SCI */
- PAD_SCI(GPIO_21, PULL_UP, EDGE_LOW),
-
- /* GPIO_24 - USB_A1_OC_ODL */
- PAD_NF(GPIO_24, USB_OC3_L, PULL_UP),
-
- /* GPIO_25 - SD_CD */
- PAD_NF(GPIO_25, SD0_CD, PULL_UP),
-
- /* GPIO_42 - S5_MUX_CTRL */
- PAD_NF(GPIO_42, S5_MUX_CTRL, PULL_NONE),
-
- /* GPIO_67 - PEN_RESET */
- PAD_GPO(GPIO_67, LOW),
-
- /* GPIO_75 - Unused (strap) (R139/R130) */
- PAD_GPI(GPIO_75, PULL_UP),
-
- /* GPIO_76 - EN_PP3300_TOUCHSCREEN */
- PAD_GPO(GPIO_76, HIGH),
-
- /* GPIO_84 - HUB_RST (Active High) */
- PAD_GPO(GPIO_84, LOW),
-
- /* GPIO_85 - TOUCHSCREEN_RST (Active High) */
- PAD_GPO(GPIO_85, LOW),
-
- /* GPIO_86 - Unused (TP109) */
- PAD_GPI(GPIO_86, PULL_UP),
-
- /* GPIO_87 - LPC_SERIRQ */
- PAD_NF(GPIO_87, SERIRQ, PULL_NONE),
-
- /* GPIO_88 - LPC_CLKRUN_L */
- PAD_NF(GPIO_88, LPC_CLKRUN_L, PULL_NONE),
-
- /* GPIO_90 - EN_PP3300_CAMERA */
- PAD_GPO(GPIO_90, HIGH),
-
- /* GPIO_91 - EN_PP3300_TRACKPAD */
- PAD_GPO(GPIO_91, HIGH),
-
- /* GPIO_93 - EMMC_RST_L */
- PAD_GPO(GPIO_93, HIGH),
-
- /* GPIO_101 - SD_WP_L */
- PAD_NF(GPIO_101, SD0_WP, PULL_DOWN),
-
- /* GPIO_102 - EN_SD_SOCKET_PWR */
- PAD_NF(GPIO_102, SD0_PWR_CTRL, PULL_DOWN),
-
- /* GPIO_113 - APU_I2C_SCL2 (Pen & Trackpad) */
- PAD_NF(GPIO_113, I2C2_SCL, PULL_UP),
-
- /* GPIO_114 - APU_I2C_SDA2 (Pen & Trackpad) */
- PAD_NF(GPIO_114, I2C2_SDA, PULL_UP),
-
- /* GPIO_115 - Unused (TP127) */
- PAD_GPI(GPIO_115, PULL_UP),
-
- /* GPIO_116 - PCIE_EMMC_CLKREQ_L */
- PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
-
- /* GPIO_118 - PCH_SPI_CS0_L */
- PAD_NF(GPIO_118, SPI_CS1_L, PULL_NONE),
-
- /* GPIO_119 - SPK_PA_EN */
- PAD_GPO(GPIO_119, HIGH),
-
- /* GPIO_126 - DMIC_CLK2_EN */
- PAD_GPO(GPIO_126, HIGH),
-
- /* GPIO_129 - APU_KBRST_L */
- PAD_NF(GPIO_129, KBRST_L, PULL_UP),
-
- /* GPIO_130 - Unused (TP55) */
- PAD_GPI(GPIO_130, PULL_UP),
-
- /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */
- PAD_GPO(GPIO_133, LOW),
-
- /* GPIO_135 - Unused (TP128) */
- PAD_GPI(GPIO_135, PULL_UP),
-
- /* GPIO_137 - AUDIO_CLK_EN (Remove in EVT?) */
- PAD_GPO(GPIO_137, HIGH),
-
- /* GPIO_140 - I2S_BCLK_R (init to func0, used for I2S) */
- PAD_NF(GPIO_140, UART1_CTS_L, PULL_NONE),
-
- /* GPIO_141 - I2S2_DATA_MIC2 (init to func0, used for I2S) */
- PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),
-
- /* GPIO_143 - I2S2_DATA (init to func0, used for I2S) */
- PAD_NF(GPIO_143, UART1_TXD, PULL_NONE),
-
- /* GPIO_144 - I2S_LR_R (init to func0, used for I2S) */
- PAD_NF(GPIO_144, UART1_INTR, PULL_NONE),
-
- /* GPIO_145 - PCH_I2C_AUDIO_SCL */
- PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),
-
- /* GPIO_146 - PCH_I2C_AUDIO_SDA */
- PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),
-
- /* GPIO_147 - PCH_I2C_H1_TPM_SCL */
- PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),
-
- /* GPIO_148 - PCH_I2C_H1_TPM_SDA */
- PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
-};
-
static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* GPIO_0 - EC_PCH_PWR_BTN_ODL */
PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),
@@ -466,25 +248,15 @@
const __weak
struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
{
- if (board_id() < 2) {
- *size = ARRAY_SIZE(gpio_set_stage_reset_old);
- return gpio_set_stage_reset_old;
- } else {
- *size = ARRAY_SIZE(gpio_set_stage_reset);
- return gpio_set_stage_reset;
- }
+ *size = ARRAY_SIZE(gpio_set_stage_reset);
+ return gpio_set_stage_reset;
}
const __weak
struct soc_amd_gpio *variant_gpio_table(size_t *size)
{
- if (board_id() < 2) {
- *size = ARRAY_SIZE(gpio_set_stage_ram_old);
- return gpio_set_stage_ram_old;
- } else {
- *size = ARRAY_SIZE(gpio_set_stage_ram);
- return gpio_set_stage_ram;
- }
+ *size = ARRAY_SIZE(gpio_set_stage_ram);
+ return gpio_set_stage_ram;
}
/*
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I71ad01f0d4c69a618d564e514ed99550b72a6b44
Gerrit-Change-Number: 26778
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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