<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26778">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/kahlee: Remove unused baseboard code<br><br>This code is no longer needed.<br><br>BUG=b:107537694<br>TEST=Build & boot on grunt<br><br>Change-Id: I71ad01f0d4c69a618d564e514ed99550b72a6b44<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c<br>M src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>2 files changed, 4 insertions(+), 329 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/26778/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c</span><br><span>index 6ed516f..648329f 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c</span><br><span>@@ -129,98 +129,6 @@</span><br><span> .DdiLinkList = (void *)DdiList</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * TODO: Remove after we're done with Grunt Proto</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static const PCIe_PORT_DESCRIPTOR PortListNoBayhub[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(0, 100%, 40%);">- PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(0, 100%, 40%);">- ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(0, 100%, 40%);">- 2, /* mDevAddress */</span><br><span style="color: hsl(0, 100%, 40%);">- 1, /* mDevFunction */</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(0, 100%, 40%);">- 0, /* mResetId */</span><br><span style="color: hsl(0, 100%, 40%);">- 0) /* mClkPmSupport */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(0, 100%, 40%);">- PortEnabled, /* mPortPresent */</span><br><span style="color: hsl(0, 100%, 40%);">- ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(0, 100%, 40%);">- 2, /* mDevAddress */</span><br><span style="color: hsl(0, 100%, 40%);">- 2, /* mDevFunction */</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_0_RST, /* mResetId */</span><br><span style="color: hsl(0, 100%, 40%);">- 0) /* mClkPmSupport */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(0, 100%, 40%);">- PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(0, 100%, 40%);">- ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(0, 100%, 40%);">- 2, /* mDevAddress */</span><br><span style="color: hsl(0, 100%, 40%);">- 3, /* mDevFunction */</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_1_RST, /* mResetId */</span><br><span style="color: hsl(0, 100%, 40%);">- 0) /* mClkPmSupport */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(0, 100%, 40%);">- PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(0, 100%, 40%);">- ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(0, 100%, 40%);">- 2, /* mDevAddress */</span><br><span style="color: hsl(0, 100%, 40%);">- 4, /* mDevFunction */</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_2_RST, /* mResetId */</span><br><span style="color: hsl(0, 100%, 40%);">- 0) /* mClkPmSupport */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">- /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(0, 100%, 40%);">- PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(0, 100%, 40%);">- ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(0, 100%, 40%);">- 2, /* mDevAddress */</span><br><span style="color: hsl(0, 100%, 40%);">- 5, /* mDevFunction */</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_3_RST, /* mResetId */</span><br><span style="color: hsl(0, 100%, 40%);">- 0) /* mClkPmSupport */</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-static const PCIe_COMPLEX_DESCRIPTOR PcieNoBayhub = {</span><br><span style="color: hsl(0, 100%, 40%);">- .Flags = DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(0, 100%, 40%);">- .SocketId = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- .PciePortList = (void *)PortListNoBayhub,</span><br><span style="color: hsl(0, 100%, 40%);">- .DdiLinkList = (void *)DdiList</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*---------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * OemCustomizeInitEarly</span><br><span>@@ -243,9 +151,4 @@</span><br><span> InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;</span><br><span> InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Completely disable Bayhub EMMC bridge on Proto with board_id 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Todo: Remove when we're done with Proto */</span><br><span style="color: hsl(0, 100%, 40%);">- if (board_id() == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- InitEarly->GnbConfig.PcieComplexList = (void *)&PcieNoBayhub;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>index c7bd6a5..e5dff77 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>@@ -27,60 +27,6 @@</span><br><span> * bootblock while GPIO pins used only by the OS should be initialized at</span><br><span> * ramstage.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct soc_amd_gpio gpio_set_stage_reset_old[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_4 - EN_PP3300_WLAN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_4, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_9 - H1_PCH_INT_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS),</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_15 - EC_IN_RW_OD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_15, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_22 - EC_SCI_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_26 - APU_PCIE_RST_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_40 - EMMC_BRIDGE_RST_L - Currently unused */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_40, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_70 - WLAN_PE_RST_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_70, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_74 - LPC_CLK0_EC_R */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_122 - APU_BIOS_FLASH_WP_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_122, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_131 - CONFIG_STRAP3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_131, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_132 - CONFIG_STRAP4 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_132, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_136 - UART_PCH_RX_DEBUG_TX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_138 - UART_PCH_TX_DEBUG_RX */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_139 - CONFIG_STRAP1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_139, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_142 - CONFIG_STRAP2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_142, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static const struct soc_amd_gpio gpio_set_stage_reset[] = {</span><br><span> /* GPIO_4 - EN_PP3300_WLAN */</span><br><span> PAD_GPO(GPIO_4, HIGH),</span><br><span>@@ -138,170 +84,6 @@</span><br><span> PAD_GPI(GPIO_142, PULL_NONE),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static const struct soc_amd_gpio gpio_set_stage_ram_old[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_0 - EC_PCH_PWR_BTN_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_1 - SYS_RST_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_2, WAKE_L, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_3 - MEM_VOLT_SEL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_3, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_7 - APU_PWROK_OD (currently not used) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_7, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_8, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_10 - SLP_S0_L (currently not used) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_SCI(GPIO_11, PULL_UP, EDGE_LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_12 - Unused (TP126) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_12, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_13 - APU_PEN_PDCT_ODL (currently not used) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_13, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_14 - APU_HP_INT_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_SCI(GPIO_14, PULL_UP, EDGE_LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_16 - USB_C0_OC_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_16, USB_OC0_L, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_17 - USB_C1_OC_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_17, USB_OC1_L, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_18 - USB_A0_OC_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_19 - APU_I2C_SCL3 (Touchscreen) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_20 - APU_I2C_SDA3 (Touchscreen) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_21 - APU_PEN_INT_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_SCI(GPIO_21, PULL_UP, EDGE_LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_24 - USB_A1_OC_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_24, USB_OC3_L, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_25 - SD_CD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_25, SD0_CD, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_42 - S5_MUX_CTRL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_42, S5_MUX_CTRL, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_67 - PEN_RESET */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_67, LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_75 - Unused (strap) (R139/R130) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_75, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_76 - EN_PP3300_TOUCHSCREEN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_76, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_84 - HUB_RST (Active High) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_84, LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_85 - TOUCHSCREEN_RST (Active High) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_85, LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_86 - Unused (TP109) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_86, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_87 - LPC_SERIRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_87, SERIRQ, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_88 - LPC_CLKRUN_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_88, LPC_CLKRUN_L, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_90 - EN_PP3300_CAMERA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_90, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_91 - EN_PP3300_TRACKPAD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_91, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_93 - EMMC_RST_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_93, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_101 - SD_WP_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_101, SD0_WP, PULL_DOWN),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_102 - EN_SD_SOCKET_PWR */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_102, SD0_PWR_CTRL, PULL_DOWN),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_113 - APU_I2C_SCL2 (Pen & Trackpad) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_113, I2C2_SCL, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_114 - APU_I2C_SDA2 (Pen & Trackpad) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_114, I2C2_SDA, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_115 - Unused (TP127) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_115, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_116 - PCIE_EMMC_CLKREQ_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_118 - PCH_SPI_CS0_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_118, SPI_CS1_L, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_119 - SPK_PA_EN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_119, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_126 - DMIC_CLK2_EN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_126, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_129 - APU_KBRST_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_129, KBRST_L, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_130 - Unused (TP55) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_130, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_133, LOW),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_135 - Unused (TP128) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_135, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_137 - AUDIO_CLK_EN (Remove in EVT?) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_137, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_140 - I2S_BCLK_R (init to func0, used for I2S) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_140, UART1_CTS_L, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_141 - I2S2_DATA_MIC2 (init to func0, used for I2S) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_143 - I2S2_DATA (init to func0, used for I2S) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_143, UART1_TXD, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_144 - I2S_LR_R (init to func0, used for I2S) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_144, UART1_INTR, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_145 - PCH_I2C_AUDIO_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_146 - PCH_I2C_AUDIO_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_147 - PCH_I2C_H1_TPM_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_148 - PCH_I2C_H1_TPM_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static const struct soc_amd_gpio gpio_set_stage_ram[] = {</span><br><span> /* GPIO_0 - EC_PCH_PWR_BTN_ODL */</span><br><span> PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),</span><br><span>@@ -466,25 +248,15 @@</span><br><span> const __weak</span><br><span> struct soc_amd_gpio *variant_early_gpio_table(size_t *size)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- if (board_id() < 2) {</span><br><span style="color: hsl(0, 100%, 40%);">- *size = ARRAY_SIZE(gpio_set_stage_reset_old);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_set_stage_reset_old;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- *size = ARRAY_SIZE(gpio_set_stage_reset);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_set_stage_reset;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = ARRAY_SIZE(gpio_set_stage_reset);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_set_stage_reset;</span><br><span> }</span><br><span> </span><br><span> const __weak</span><br><span> struct soc_amd_gpio *variant_gpio_table(size_t *size)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- if (board_id() < 2) {</span><br><span style="color: hsl(0, 100%, 40%);">- *size = ARRAY_SIZE(gpio_set_stage_ram_old);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_set_stage_ram_old;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- *size = ARRAY_SIZE(gpio_set_stage_ram);</span><br><span style="color: hsl(0, 100%, 40%);">- return gpio_set_stage_ram;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = ARRAY_SIZE(gpio_set_stage_ram);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_set_stage_ram;</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26778">change 26778</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26778"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I71ad01f0d4c69a618d564e514ed99550b72a6b44 </div>
<div style="display:none"> Gerrit-Change-Number: 26778 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>