[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Add Page table mapping for System Memory

[Hannah Williams (Code Review)]

Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/26745


Change subject: soc/intel/apollolake: Add Page table mapping for System Memory
......................................................................

soc/intel/apollolake: Add Page table mapping for System Memory

Since we do not know before hand the memory range initialized by FSP memory
init until it completes and as memory gets accessed from within FSP memory
init to migrate FSP from CAR to memory, we need to add this mapping in
coreboot.

Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
M src/soc/intel/apollolake/glk_page_map.txt
M src/soc/intel/apollolake/romstage.c
2 files changed, 1 insertion(+), 43 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/26745/1

diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt
index e4c51b0..a4844ef 100644
--- a/src/soc/intel/apollolake/glk_page_map.txt
+++ b/src/soc/intel/apollolake/glk_page_map.txt
@@ -1,3 +1,4 @@
+0x00000000, 0x100000000, WB, # RAM
 0xd0000000, 0x100000000, UC, NX # All of MMIO
 # Maximum 16MiB of mmio SPI flash decode.
 0xff000000, 0x100000000, WP, # memory-mapped SPI
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index cee23b6..c50134f 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -248,13 +248,6 @@
 	tseg_base = (uintptr_t)smm_base;
 	postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
 
-	/* Ensure TSEG has mappings. */
-	if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)) {
-		if (paging_identity_map_addr(tseg_base, smm_size, PAT_WB))
-			printk(BIOS_ERR, "Unable to map TSEG: %lx--%lx\n",
-				tseg_base, tseg_base + smm_size);
-	}
-
 	run_postcar_phase(&pcf);
 }
 
@@ -343,40 +336,6 @@
 #endif
 }
 
-static void prepare_fspm_pages(void)
-{
-	const size_t mib128 = 128 * MiB;
-	uintptr_t base;
-	/* All in units of MiB */
-	size_t mem_sz;
-	size_t iohole_sz;
-	size_t low_mem_sz;
-
-	mem_sz = memory_in_system_in_mib();
-
-	if (!mem_sz) {
-		printk(BIOS_ERR, "No memory in system! FSP will hang...\n");
-		return;
-	}
-
-	iohole_sz = iohole_in_mib();
-
-	/* Mark pages as WB where FSP will write. One region will be in cbmem,
-	   but it's not clear what else FSP is writing to. Try to make the best
-	   calculation. */
-	low_mem_sz = 4 * (GiB / MiB) - iohole_sz;
-
-	if (low_mem_sz > mem_sz)
-		low_mem_sz = mem_sz;
-
-	/* Assume all accesses are within 128MiB of the crude low memory
-	   calculation above. */
-	base = low_mem_sz * MiB - mib128;
-	if (paging_identity_map_addr(base, mib128, PAT_WB))
-		printk(BIOS_ERR, "Unable to map %lx--%lx\n", base,
-			base + mib128);
-}
-
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	struct region_device rdev;
@@ -430,8 +389,6 @@
 
 	car_set_var(fsp_version, version);
 
-	if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM))
-		prepare_fspm_pages();
 }
 
 __weak

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e
Gerrit-Change-Number: 26745
Gerrit-PatchSet: 1
Gerrit-Owner: Hannah Williams <hannah.williams at intel.com>
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