<p>Hannah Williams has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26745">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Add Page table mapping for System Memory<br><br>Since we do not know before hand the memory range initialized by FSP memory<br>init until it completes and as memory gets accessed from within FSP memory<br>init to migrate FSP from CAR to memory, we need to add this mapping in<br>coreboot.<br><br>Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e<br>Signed-off-by: Hannah Williams <hannah.williams@intel.com><br>---<br>M src/soc/intel/apollolake/glk_page_map.txt<br>M src/soc/intel/apollolake/romstage.c<br>2 files changed, 1 insertion(+), 43 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/26745/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt</span><br><span>index e4c51b0..a4844ef 100644</span><br><span>--- a/src/soc/intel/apollolake/glk_page_map.txt</span><br><span>+++ b/src/soc/intel/apollolake/glk_page_map.txt</span><br><span>@@ -1,3 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+0x00000000, 0x100000000, WB, # RAM</span><br><span> 0xd0000000, 0x100000000, UC, NX # All of MMIO</span><br><span> # Maximum 16MiB of mmio SPI flash decode.</span><br><span> 0xff000000, 0x100000000, WP, # memory-mapped SPI</span><br><span>diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c</span><br><span>index cee23b6..c50134f 100644</span><br><span>--- a/src/soc/intel/apollolake/romstage.c</span><br><span>+++ b/src/soc/intel/apollolake/romstage.c</span><br><span>@@ -248,13 +248,6 @@</span><br><span> tseg_base = (uintptr_t)smm_base;</span><br><span> postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Ensure TSEG has mappings. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (paging_identity_map_addr(tseg_base, smm_size, PAT_WB))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Unable to map TSEG: %lx--%lx\n",</span><br><span style="color: hsl(0, 100%, 40%);">- tseg_base, tseg_base + smm_size);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> run_postcar_phase(&pcf);</span><br><span> }</span><br><span> </span><br><span>@@ -343,40 +336,6 @@</span><br><span> #endif</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void prepare_fspm_pages(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const size_t mib128 = 128 * MiB;</span><br><span style="color: hsl(0, 100%, 40%);">- uintptr_t base;</span><br><span style="color: hsl(0, 100%, 40%);">- /* All in units of MiB */</span><br><span style="color: hsl(0, 100%, 40%);">- size_t mem_sz;</span><br><span style="color: hsl(0, 100%, 40%);">- size_t iohole_sz;</span><br><span style="color: hsl(0, 100%, 40%);">- size_t low_mem_sz;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mem_sz = memory_in_system_in_mib();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!mem_sz) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "No memory in system! FSP will hang...\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- iohole_sz = iohole_in_mib();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Mark pages as WB where FSP will write. One region will be in cbmem,</span><br><span style="color: hsl(0, 100%, 40%);">- but it's not clear what else FSP is writing to. Try to make the best</span><br><span style="color: hsl(0, 100%, 40%);">- calculation. */</span><br><span style="color: hsl(0, 100%, 40%);">- low_mem_sz = 4 * (GiB / MiB) - iohole_sz;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (low_mem_sz > mem_sz)</span><br><span style="color: hsl(0, 100%, 40%);">- low_mem_sz = mem_sz;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Assume all accesses are within 128MiB of the crude low memory</span><br><span style="color: hsl(0, 100%, 40%);">- calculation above. */</span><br><span style="color: hsl(0, 100%, 40%);">- base = low_mem_sz * MiB - mib128;</span><br><span style="color: hsl(0, 100%, 40%);">- if (paging_identity_map_addr(base, mib128, PAT_WB))</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Unable to map %lx--%lx\n", base,</span><br><span style="color: hsl(0, 100%, 40%);">- base + mib128);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)</span><br><span> {</span><br><span> struct region_device rdev;</span><br><span>@@ -430,8 +389,6 @@</span><br><span> </span><br><span> car_set_var(fsp_version, version);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM))</span><br><span style="color: hsl(0, 100%, 40%);">- prepare_fspm_pages();</span><br><span> }</span><br><span> </span><br><span> __weak</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26745">change 26745</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26745"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e </div>
<div style="display:none"> Gerrit-Change-Number: 26745 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Hannah Williams <hannah.williams@intel.com> </div>