[coreboot-gerrit] Change in coreboot[master]: mainboard/opencellular/rotundu: Add supabrck EMMC support

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27684


Change subject: mainboard/opencellular/rotundu: Add supabrck EMMC support
......................................................................

mainboard/opencellular/rotundu: Add supabrck EMMC support

Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43
Signed-off-by: Philipp Deppenwiese <zaolin at das-labor.org>
---
M src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb
M src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
2 files changed, 16 insertions(+), 13 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27684/1

diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb
index a31a001..df08922 100644
--- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb
+++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb
@@ -26,7 +26,7 @@
 	register "PcdMrcInitSPDAddr1"      = "0xa0"
 	register "PcdMrcInitSPDAddr2"      = "0xa2"
 	register "PcdMrcInitMmioSize"      = "MMIO_SIZE_DEFAULT"
-	register "PcdeMMCBootMode"         = "EMMC_DISABLED"
+	register "PcdeMMCBootMode"         = "EMMC_FOLLOWS_DEVICETREE"
 	register "PcdIgdDvmt50PreAlloc"    = "IGD_MEMSIZE_DEFAULT"
 	register "PcdApertureSize"         = "APERTURE_SIZE_DEFAULT"
 	register "PcdGttSize"              = "GTT_SIZE_DEFAULT"
@@ -53,7 +53,7 @@
 		device pci 14.0 on end	# 8086 0F35 - USB XHCI - Only 1 USB controller at a time
 		device pci 15.0 off end	# 8086 0F28 - LP Engine Audio
 		device pci 16.0 off end # 8086 0F37 - OTG controller
-		device pci 17.0 off end	# 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
+		device pci 17.0 on end	# 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
 		device pci 18.0 on end	# 8086 0F40 - SIO - DMA
 		device pci 18.1 on end	# 8086 0F41 -   I2C Port 1
 		device pci 18.2 off end	# 8086 0F42 -   I2C Port 2
diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
index 78d1ad6..c9d5426 100644
--- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
+++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c
@@ -19,6 +19,9 @@
 #include <soc/gpio.h>
 #include "../../irqroute.h"
 
+#define GPIO_FUNC3_PULL_UP_20K          GPIO_FUNC(3, PULL_UP, 20K)
+#define GPIO_FUNC3_PULL_DOWN_20K        GPIO_FUNC(3, PULL_DOWN, 20K)
+
 /* NCORE GPIOs */
 static const struct soc_gpio_map gpncore_gpio_map[] = {
 
@@ -85,27 +88,27 @@
 	/* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/
 	GPIO_DEFAULT,
 	/* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/
-	GPIO_NC,
+	GPIO_FUNC3_PULL_DOWN_20K,
 	/* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_UP_20K,
 	/* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_UP_20K,
 	/* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_UP_20K,
 	/* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_UP_20K,
 	/* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_UP_20K,
 	/* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_UP_20K,
 	/* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_UP_20K,
 	/* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_UP_20K,
 	/* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_UP_20K,
 	/* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */
-	GPIO_NC,
+	GPIO_FUNC3_PULL_DOWN_20K,
 	/* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */
 	GPIO_NC,
 	/* GPIO_S0_SC[027] SD2_CLK */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43
Gerrit-Change-Number: 27684
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
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