<p>Philipp Deppenwiese has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27684">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/opencellular/rotundu: Add supabrck EMMC support<br><br>Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43<br>Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org><br>---<br>M src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb<br>M src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c<br>2 files changed, 16 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27684/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb</span><br><span>index a31a001..df08922 100644</span><br><span>--- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb</span><br><span>+++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb</span><br><span>@@ -26,7 +26,7 @@</span><br><span>    register "PcdMrcInitSPDAddr1"      = "0xa0"</span><br><span>      register "PcdMrcInitSPDAddr2"      = "0xa2"</span><br><span>      register "PcdMrcInitMmioSize"      = "MMIO_SIZE_DEFAULT"</span><br><span style="color: hsl(0, 100%, 40%);">-    register "PcdeMMCBootMode"         = "EMMC_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+      register "PcdeMMCBootMode"         = "EMMC_FOLLOWS_DEVICETREE"</span><br><span>   register "PcdIgdDvmt50PreAlloc"    = "IGD_MEMSIZE_DEFAULT"</span><br><span>       register "PcdApertureSize"         = "APERTURE_SIZE_DEFAULT"</span><br><span>     register "PcdGttSize"              = "GTT_SIZE_DEFAULT"</span><br><span>@@ -53,7 +53,7 @@</span><br><span>              device pci 14.0 on end  # 8086 0F35 - USB XHCI - Only 1 USB controller at a time</span><br><span>             device pci 15.0 off end # 8086 0F28 - LP Engine Audio</span><br><span>                device pci 16.0 off end # 8086 0F37 - OTG controller</span><br><span style="color: hsl(0, 100%, 40%);">-            device pci 17.0 off end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time</span><br><span style="color: hsl(120, 100%, 40%);">+          device pci 17.0 on end  # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time</span><br><span>                 device pci 18.0 on end  # 8086 0F40 - SIO - DMA</span><br><span>              device pci 18.1 on end  # 8086 0F41 -   I2C Port 1</span><br><span>           device pci 18.2 off end # 8086 0F42 -   I2C Port 2</span><br><span>diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c</span><br><span>index 78d1ad6..c9d5426 100644</span><br><span>--- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c</span><br><span>+++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c</span><br><span>@@ -19,6 +19,9 @@</span><br><span> #include <soc/gpio.h></span><br><span> #include "../../irqroute.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_FUNC3_PULL_UP_20K          GPIO_FUNC(3, PULL_UP, 20K)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_FUNC3_PULL_DOWN_20K        GPIO_FUNC(3, PULL_DOWN, 20K)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* NCORE GPIOs */</span><br><span> static const struct soc_gpio_map gpncore_gpio_map[] = {</span><br><span> </span><br><span>@@ -85,27 +88,27 @@</span><br><span>    /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/</span><br><span>   GPIO_DEFAULT,</span><br><span>        /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/</span><br><span style="color: hsl(0, 100%, 40%);">-       GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_DOWN_20K,</span><br><span>    /* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">-      GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_UP_20K,</span><br><span>      /* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */</span><br><span style="color: hsl(0, 100%, 40%);">-    GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_UP_20K,</span><br><span>      /* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */</span><br><span style="color: hsl(0, 100%, 40%);">-    GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_UP_20K,</span><br><span>      /* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */</span><br><span style="color: hsl(0, 100%, 40%);">-    GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_UP_20K,</span><br><span>      /* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */</span><br><span style="color: hsl(0, 100%, 40%);">-    GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_UP_20K,</span><br><span>      /* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */</span><br><span style="color: hsl(0, 100%, 40%);">-    GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_UP_20K,</span><br><span>      /* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */</span><br><span style="color: hsl(0, 100%, 40%);">-    GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_UP_20K,</span><br><span>      /* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */</span><br><span style="color: hsl(0, 100%, 40%);">-    GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_UP_20K,</span><br><span>      /* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */</span><br><span style="color: hsl(0, 100%, 40%);">-    GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_UP_20K,</span><br><span>      /* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */</span><br><span style="color: hsl(0, 100%, 40%);">-      GPIO_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+      GPIO_FUNC3_PULL_DOWN_20K,</span><br><span>    /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */</span><br><span>  GPIO_NC,</span><br><span>     /* GPIO_S0_SC[027] SD2_CLK */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27684">change 27684</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27684"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43 </div>
<div style="display:none"> Gerrit-Change-Number: 27684 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>