[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Fix watchdog

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27669


Change subject: sb/intel/bd82x6x: Fix watchdog
......................................................................

sb/intel/bd82x6x: Fix watchdog

* Fix comments
* Use defines instead of magic values
* Use new PMBASE API to modify registers

Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
---
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/watchdog.c
2 files changed, 24 insertions(+), 20 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27669/1

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7c7e0ed..65aac55 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -503,9 +503,12 @@
 #define SS_CNT		0x50
 #define C3_RES		0x54
 #define TCO1_STS	0x64
+#define   TCO1_TIMEOUT	(1 << 3)
 #define   DMISCI_STS	(1 << 9)
 #define TCO2_STS	0x66
+#define   SECOND_TO_STS	(1 << 1)
 #define TCO1_CNT	0x68
+#define   TCO_TMR_HLT	(1 << 11)
 #define   TCO_LOCK	(1 << 12)
 #define TCO2_CNT	0x6a
 
diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c
index 9a867e4..eb4d38c 100644
--- a/src/southbridge/intel/bd82x6x/watchdog.c
+++ b/src/southbridge/intel/bd82x6x/watchdog.c
@@ -19,37 +19,38 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
+#include <southbridge/intel/common/pmbase.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
 #include <watchdog.h>
 
-  //
-  //  Disable PCH Watchdog timer at SB_RCBA+0x3410
-  //
-  //  Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20;
-  //
+/*
+ *  Disable PCH watchdog timer
+ */
 void watchdog_off(void)
 {
+	unsigned int value;
 	struct device *dev;
-	unsigned long value, base;
 
-	/* Turn off the ICH7 watchdog. */
+	/* Get LPC device. */
 	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 
-	/* Enable I/O space. */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
-
-	/* Get TCO base. */
-	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+	/* Disable interrupt. */
+	value = pci_read_config16(dev, PCI_COMMAND);
+	value |= PCI_COMMAND_INT_DISABLE;
+	pci_write_config16(dev, PCI_COMMAND, value);
 
 	/* Disable the watchdog timer. */
-	value = inw(base + 0x08);
-	value |= 1 << 11;
-	outw(value, base + 0x08);
+	value = read_pmbase16(TCO1_CNT);
+	value |= TCO_TMR_HLT;
+	write_pmbase16(TCO1_CNT, value);
 
 	/* Clear TCO timeout status. */
-	outw(0x0008, base + 0x04);
-	outw(0x0002, base + 0x06);
+	write_pmbase16(TCO1_STS, TCO1_TIMEOUT);
+	write_pmbase16(TCO2_STS, SECOND_TO_STS);
 
-	printk(BIOS_DEBUG, "PCH watchdog disabled\n");
+	/* FIXME: Set RCBA GCS Bit5 "No Reboot" ? */
+
+	printk(BIOS_DEBUG, "PCH: watchdog disabled\n");
 }

-- 
To view, visit https://review.coreboot.org/27669
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512
Gerrit-Change-Number: 27669
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180727/9e5a6ab1/attachment.html>