<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27669">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/bd82x6x: Fix watchdog<br><br>* Fix comments<br>* Use defines instead of magic values<br>* Use new PMBASE API to modify registers<br><br>Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/southbridge/intel/bd82x6x/pch.h<br>M src/southbridge/intel/bd82x6x/watchdog.c<br>2 files changed, 24 insertions(+), 20 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27669/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index 7c7e0ed..65aac55 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -503,9 +503,12 @@</span><br><span> #define SS_CNT           0x50</span><br><span> #define C3_RES          0x54</span><br><span> #define TCO1_STS        0x64</span><br><span style="color: hsl(120, 100%, 40%);">+#define   TCO1_TIMEOUT    (1 << 3)</span><br><span> #define   DMISCI_STS  (1 << 9)</span><br><span> #define TCO2_STS      0x66</span><br><span style="color: hsl(120, 100%, 40%);">+#define   SECOND_TO_STS   (1 << 1)</span><br><span> #define TCO1_CNT      0x68</span><br><span style="color: hsl(120, 100%, 40%);">+#define   TCO_TMR_HLT     (1 << 11)</span><br><span> #define   TCO_LOCK   (1 << 12)</span><br><span> #define TCO2_CNT     0x6a</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c</span><br><span>index 9a867e4..eb4d38c 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/watchdog.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/watchdog.c</span><br><span>@@ -19,37 +19,38 @@</span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/pmbase.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #include <watchdog.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  //</span><br><span style="color: hsl(0, 100%, 40%);">-  //  Disable PCH Watchdog timer at SB_RCBA+0x3410</span><br><span style="color: hsl(0, 100%, 40%);">-  //</span><br><span style="color: hsl(0, 100%, 40%);">-  //  Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20;</span><br><span style="color: hsl(0, 100%, 40%);">-  //</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ *  Disable PCH watchdog timer</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> void watchdog_off(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+  unsigned int value;</span><br><span>  struct device *dev;</span><br><span style="color: hsl(0, 100%, 40%);">-     unsigned long value, base;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-  /* Turn off the ICH7 watchdog. */</span><br><span style="color: hsl(120, 100%, 40%);">+     /* Get LPC device. */</span><br><span>        dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable I/O space. */</span><br><span style="color: hsl(0, 100%, 40%);">- value = pci_read_config16(dev, 0x04);</span><br><span style="color: hsl(0, 100%, 40%);">-   value |= (1 << 10);</span><br><span style="color: hsl(0, 100%, 40%);">-       pci_write_config16(dev, 0x04, value);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-   /* Get TCO base. */</span><br><span style="color: hsl(0, 100%, 40%);">-     base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;</span><br><span style="color: hsl(120, 100%, 40%);">+   /* Disable interrupt. */</span><br><span style="color: hsl(120, 100%, 40%);">+      value = pci_read_config16(dev, PCI_COMMAND);</span><br><span style="color: hsl(120, 100%, 40%);">+  value |= PCI_COMMAND_INT_DISABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+     pci_write_config16(dev, PCI_COMMAND, value);</span><br><span> </span><br><span>     /* Disable the watchdog timer. */</span><br><span style="color: hsl(0, 100%, 40%);">-       value = inw(base + 0x08);</span><br><span style="color: hsl(0, 100%, 40%);">-       value |= 1 << 11;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(value, base + 0x08);</span><br><span style="color: hsl(120, 100%, 40%);">+     value = read_pmbase16(TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+      value |= TCO_TMR_HLT;</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase16(TCO1_CNT, value);</span><br><span> </span><br><span>         /* Clear TCO timeout status. */</span><br><span style="color: hsl(0, 100%, 40%);">- outw(0x0008, base + 0x04);</span><br><span style="color: hsl(0, 100%, 40%);">-      outw(0x0002, base + 0x06);</span><br><span style="color: hsl(120, 100%, 40%);">+    write_pmbase16(TCO1_STS, TCO1_TIMEOUT);</span><br><span style="color: hsl(120, 100%, 40%);">+       write_pmbase16(TCO2_STS, SECOND_TO_STS);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    printk(BIOS_DEBUG, "PCH watchdog disabled\n");</span><br><span style="color: hsl(120, 100%, 40%);">+      /* FIXME: Set RCBA GCS Bit5 "No Reboot" ? */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+      printk(BIOS_DEBUG, "PCH: watchdog disabled\n");</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27669">change 27669</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27669"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512 </div>
<div style="display:none"> Gerrit-Change-Number: 27669 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>