[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy/variants/nocturne: enable FPMCU power

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/27658


Change subject: mb/google/poppy/variants/nocturne: enable FPMCU power
......................................................................

mb/google/poppy/variants/nocturne: enable FPMCU power

Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.

BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.

Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro at google.com>
---
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/gpio.c
2 files changed, 3 insertions(+), 10 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27658/1

diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 235391e..9d9c5ae 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -423,15 +423,8 @@
 				register "compat_string" = ""google,cros-ec-spi""
 				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)"
 				register "wake" = "GPE0_DW0_09" # GPP_C9
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
-				register "reset_delay_ms" = "0"
-				register "reset_off_delay_ms" = "0"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
-				register "enable_delay_ms" = "0"
-				register "enable_off_delay_ms" = "0"
-				register "has_power_resource" = "1"
 				device spi 0 on end
-			end
+			end # FPMCU
 		end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index 3c186c7..782ce00 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -38,7 +38,7 @@
 	/* A10 : CLKOUT_LPC1 ==> NC */
 	PAD_CFG_NC(GPP_A10),
 	/* A11 : PCH_FP_PWR_EN */
-	PAD_CFG_GPO(GPP_A11, 0, DEEP),
+	PAD_CFG_GPO(GPP_A11, 1, DEEP),
 	/* A12 : ISH_GP6 */
 	PAD_CFG_NC(GPP_A12),
 	/* A13 : SUSWARN# ==> SUSWARN_L */
@@ -133,7 +133,7 @@
 	/* C9  : UART0_TXD ==> FPMCU_INT */
 	PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT),
 	/* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */
-	PAD_CFG_GPO(GPP_C10, 0, DEEP),
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
 	/* C11 : UART0_CTS# ==> FPMCU_INT */
 	PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, DEEP),
 	/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */

-- 
To view, visit https://review.coreboot.org/27658
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Gerrit-Change-Number: 27658
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180727/7af94085/attachment.html>