<p>Nick Vaccaro has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27658">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variants/nocturne: enable FPMCU power<br><br>Enable power to FPMCU by default on power-on and deassert<br>the PCH_FPMCU_RST_ODL reset line.<br><br>BUG=b:111880258<br>BRANCH=none<br>TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot<br>nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel<br>prompt, wait a few seconds, press power button to wake, then execute<br>"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes<br>up empty.<br><br>Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289<br>Signed-off-by: Nick Vaccaro <nvaccaro@google.com><br>---<br>M src/mainboard/google/poppy/variants/nocturne/devicetree.cb<br>M src/mainboard/google/poppy/variants/nocturne/gpio.c<br>2 files changed, 3 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27658/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>index 235391e..9d9c5ae 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>@@ -423,15 +423,8 @@</span><br><span>                                register "compat_string" = ""google,cros-ec-spi""</span><br><span>                              register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)"</span><br><span>                               register "wake" = "GPE0_DW0_09" # GPP_C9</span><br><span style="color: hsl(0, 100%, 40%);">-                            register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"</span><br><span style="color: hsl(0, 100%, 40%);">-                              register "reset_delay_ms" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-                             register "reset_off_delay_ms" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-                         register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"</span><br><span style="color: hsl(0, 100%, 40%);">-                            register "enable_delay_ms" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-                            register "enable_off_delay_ms" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-                                register "has_power_resource" = "1"</span><br><span>                              device spi 0 on end</span><br><span style="color: hsl(0, 100%, 40%);">-                     end</span><br><span style="color: hsl(120, 100%, 40%);">+                   end # FPMCU</span><br><span>          end # GSPI #1</span><br><span>                device pci 1e.4 on  end # eMMC</span><br><span>               device pci 1e.5 off end # SDIO</span><br><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c</span><br><span>index 3c186c7..782ce00 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span>  /* A10 : CLKOUT_LPC1 ==> NC */</span><br><span>    PAD_CFG_NC(GPP_A10),</span><br><span>         /* A11 : PCH_FP_PWR_EN */</span><br><span style="color: hsl(0, 100%, 40%);">-       PAD_CFG_GPO(GPP_A11, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+        PAD_CFG_GPO(GPP_A11, 1, DEEP),</span><br><span>       /* A12 : ISH_GP6 */</span><br><span>  PAD_CFG_NC(GPP_A12),</span><br><span>         /* A13 : SUSWARN# ==> SUSWARN_L */</span><br><span>@@ -133,7 +133,7 @@</span><br><span>  /* C9  : UART0_TXD ==> FPMCU_INT */</span><br><span>       PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT),</span><br><span>    /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_C10, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+        PAD_CFG_GPO(GPP_C10, 1, DEEP),</span><br><span>       /* C11 : UART0_CTS# ==> FPMCU_INT */</span><br><span>      PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, DEEP),</span><br><span>     /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27658">change 27658</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27658"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289 </div>
<div style="display:none"> Gerrit-Change-Number: 27658 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>