[coreboot-gerrit] Change in coreboot[master]: nb/amd/pi/00730F01: Add initial native IVRS support

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/15164 )

Change subject: nb/amd/pi/00730F01: Add initial native IVRS support
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Patch Set 18:

(18 comments)

https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c
File src/northbridge/amd/pi/00730F01/northbridge.c:

https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@457
PS18, Line 457: 		if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) {
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@457
PS18, Line 457: 		if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) {
braces {} are not necessary for single statement blocks


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@485
PS18, Line 485: 					   && (dev->path.pci.devfn < (0x3 << 3))) {
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@541
PS18, Line 541: 				if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@543
PS18, Line 543: 					if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@562
PS18, Line 562: 						/* Device is legacy PCI or PCI-X */
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@583
PS18, Line 583: 				} else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@584
PS18, Line 584: 					if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@609
PS18, Line 609: 		for (sibling = link->children; sibling; sibling = sibling->sibling)
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@610
PS18, Line 610: 			add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length);
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@615
PS18, Line 615: unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
"foo* bar" should be "foo *bar"


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@652
PS18, Line 652: static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current)
"foo* bar" should be "foo *bar"


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@658
PS18, Line 658: 		printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate G-series northbridge device!  IVRS table not generated...\n");
Prefer using '"%s...", __func__' to using 'acpi_fill_ivrs', this function's name, in a string


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@663
PS18, Line 663: 	ivrs->iv_info |= (0x40 << 15);	/* Maximum supported virtual address size */
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@664
PS18, Line 664: 	ivrs->iv_info |= (0x30 << 8);	/* Maximum supported physical address size */
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@669
PS18, Line 669: 	ivrs->ivhd.flags |= 0x10;					/* Enable ATS support */
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@671
PS18, Line 671: 	ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8);	/* BDF <bus>:00.2 */
line over 80 characters


https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@672
PS18, Line 672: 	ivrs->ivhd.capability_offset = 0x40;				/* Capability block 0x40 (type 0xf, "Secure device") */
line over 80 characters



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4
Gerrit-Change-Number: 15164
Gerrit-PatchSet: 18
Gerrit-Owner: Timothy Pearson <tpearson at raptorengineering.com>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-Reviewer: Timothy Pearson <tpearson at raptorengineering.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Piotr Król <piotr.krol at 3mdeb.com>
Gerrit-Comment-Date: Tue, 24 Jul 2018 14:53:26 +0000
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