<p><a href="https://review.coreboot.org/15164">View Change</a></p><p>18 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c">File src/northbridge/amd/pi/00730F01/northbridge.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@457">Patch Set #18, Line 457:</a> <code style="font-family:monospace,monospace"> if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@457">Patch Set #18, Line 457:</a> <code style="font-family:monospace,monospace"> if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@485">Patch Set #18, Line 485:</a> <code style="font-family:monospace,monospace"> && (dev->path.pci.devfn < (0x3 << 3))) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@541">Patch Set #18, Line 541:</a> <code style="font-family:monospace,monospace"> if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@543">Patch Set #18, Line 543:</a> <code style="font-family:monospace,monospace"> if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@562">Patch Set #18, Line 562:</a> <code style="font-family:monospace,monospace"> /* Device is legacy PCI or PCI-X */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@583">Patch Set #18, Line 583:</a> <code style="font-family:monospace,monospace"> } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@584">Patch Set #18, Line 584:</a> <code style="font-family:monospace,monospace"> if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@609">Patch Set #18, Line 609:</a> <code style="font-family:monospace,monospace"> for (sibling = link->children; sibling; sibling = sibling->sibling)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@610">Patch Set #18, Line 610:</a> <code style="font-family:monospace,monospace"> add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@615">Patch Set #18, Line 615:</a> <code style="font-family:monospace,monospace">unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">"foo* bar" should be "foo *bar"</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@652">Patch Set #18, Line 652:</a> <code style="font-family:monospace,monospace">static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">"foo* bar" should be "foo *bar"</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@658">Patch Set #18, Line 658:</a> <code style="font-family:monospace,monospace"> printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate G-series northbridge device! IVRS table not generated...\n");</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Prefer using '"%s...", __func__' to using 'acpi_fill_ivrs', this function's name, in a string</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@663">Patch Set #18, Line 663:</a> <code style="font-family:monospace,monospace"> ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@664">Patch Set #18, Line 664:</a> <code style="font-family:monospace,monospace"> ivrs->iv_info |= (0x30 << 8); /* Maximum supported physical address size */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@669">Patch Set #18, Line 669:</a> <code style="font-family:monospace,monospace"> ivrs->ivhd.flags |= 0x10; /* Enable ATS support */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@671">Patch Set #18, Line 671:</a> <code style="font-family:monospace,monospace"> ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/15164/18/src/northbridge/amd/pi/00730F01/northbridge.c@672">Patch Set #18, Line 672:</a> <code style="font-family:monospace,monospace"> ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/15164">change 15164</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/15164"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 </div>
<div style="display:none"> Gerrit-Change-Number: 15164 </div>
<div style="display:none"> Gerrit-PatchSet: 18 </div>
<div style="display:none"> Gerrit-Owner: Timothy Pearson <tpearson@raptorengineering.com> </div>
<div style="display:none"> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Timothy Pearson <tpearson@raptorengineering.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-CC: Piotr Król <piotr.krol@3mdeb.com> </div>
<div style="display:none"> Gerrit-Comment-Date: Tue, 24 Jul 2018 14:53:26 +0000 </div>
<div style="display:none"> Gerrit-HasComments: Yes </div>
<div style="display:none"> Gerrit-HasLabels: No </div>