[coreboot-gerrit] Change in coreboot[master]: cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sat Jul 21 15:12:04 CEST 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27585
Change subject: cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x
......................................................................
cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
the SMRR MSR are at a different offset for model_6fx and model_1067x.
This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL.
Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/include/cpu/x86/mtrr.h
2 files changed, 31 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/27585/1
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index e3cb11b..fc9e36a 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -57,12 +57,28 @@
static struct smm_relocation_params smm_reloc_params;
static void *default_smm_area = NULL;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
+static void write_smrr(struct smm_relocation_params *relo_params)
{
+ struct cpuinfo_x86 c;
+
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask);
+ /* model_6fx and model_1067x have a different msr */
+ get_fms(&c, cpuid_eax(1));
+ if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) {
+ msr_t msr;
+ msr = rdmsr(MSR_FEATURE_CONTROL);
+ /* SMRR enabled and feature locked */
+ if (!((msr.lo & (1 << 3)) && (msr.lo & (1 <<0)))) {
+ printk(BIOS_WARNING, "SMRR not enabled, skip writing SMRR...\n");
+ return;
+ }
+ wrmsr(MSR_SMRR_PHYSBASE, relo_params->smrr_base);
+ wrmsr(MSR_SMRR_PHYSMASK, relo_params->smrr_mask);
+ } else {
+ wrmsr(IA32_SMRR_PHYSBASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYSMASK, relo_params->smrr_mask);
+ }
}
/* The relocation work is actually performed in SMM context, but the code
@@ -137,7 +153,14 @@
params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
/* SMRR has 32-bits of valid address aligned to 4KiB. */
- params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+ struct cpuinfo_x86 c;
+
+ /* for model_6fx and model_1067x byte [0:11] on smrr_base are reserved */
+ get_fms(&c, cpuid_eax(1));
+ if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
+ params->smrr_base.lo = (params->smram_base & rmask);
+ else
+ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
| MTRR_PHYS_MASK_VALID;
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 58a3ce5..be2bfa9 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -31,6 +31,10 @@
#define IA32_SMRR_PHYSBASE 0x1f2
#define IA32_SMRR_PHYSMASK 0x1f3
+#define MSR_FEATURE_CONTROL 0x3a
+#define MSR_SMRR_PHYSBASE 0xa0
+#define MSR_SMRR_PHYSMASK 0xa1
+
#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
#define MTRR_PHYS_MASK_VALID (1 << 11)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9
Gerrit-Change-Number: 27585
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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