[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy/variants/nocturne: set nvme to use clk src 3

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27536 )

Change subject: mb/google/poppy/variants/nocturne: set nvme to use clk src 3
......................................................................

mb/google/poppy/variants/nocturne: set nvme to use clk src 3

Latest nocturne architecture uses clk src 3 for nvme.

BUG=b:111514174
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage" and verify nvme
nocturne devices are able to recognize the nvme controller.

Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1
Signed-off-by: Nick Vaccaro <nvaccaro at google.com>
Reviewed-on: https://review.coreboot.org/27536
Reviewed-by: Lijian Zhao <lijian.zhao at intel.com>
Reviewed-by: Furquan Shaikh <furquan at google.com>
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
---
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Lijian Zhao: Looks good to me, approved



diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 5e1b7aa..1d00bc2 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -164,13 +164,13 @@
         #  PcieRpEnable:                 Enable root port
         #  PcieRpClkReqSupport:          Enable CLKREQ#
         #  PcieRpClkReqNumber:           Uses SRCCLKREQ2#
-        #  PcieRpClkSrcNumber:           Uses 2
+        #  PcieRpClkSrcNumber:           Uses 3
         #  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
         #  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
         register "PcieRpEnable[8]" = "1"
         register "PcieRpClkReqSupport[8]" = "1"
         register "PcieRpClkReqNumber[8]" = "2"
-        register "PcieRpClkSrcNumber[8]" = "2"
+        register "PcieRpClkSrcNumber[8]" = "3"
         register "PcieRpAdvancedErrorReporting[8]" = "1"
         register "PcieRpLtrEnable[8]" = "1"
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1
Gerrit-Change-Number: 27536
Gerrit-PatchSet: 2
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
Gerrit-Reviewer: Caveh Jalali <caveh at google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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