<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/27536">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Lijian Zhao: Looks good to me, approved

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variants/nocturne: set nvme to use clk src 3<br><br>Latest nocturne architecture uses clk src 3 for nvme.<br><br>BUG=b:111514174<br>BRANCH=none<br>TEST="emerge-nocturne coreboot chromeos-bootimage" and verify nvme<br>nocturne devices are able to recognize the nvme controller.<br><br>Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1<br>Signed-off-by: Nick Vaccaro <nvaccaro@google.com><br>Reviewed-on: https://review.coreboot.org/27536<br>Reviewed-by: Lijian Zhao <lijian.zhao@intel.com><br>Reviewed-by: Furquan Shaikh <furquan@google.com><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M src/mainboard/google/poppy/variants/nocturne/devicetree.cb<br>1 file changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>index 5e1b7aa..1d00bc2 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb</span><br><span>@@ -164,13 +164,13 @@</span><br><span>         #  PcieRpEnable:                 Enable root port</span><br><span>         #  PcieRpClkReqSupport:          Enable CLKREQ#</span><br><span>         #  PcieRpClkReqNumber:           Uses SRCCLKREQ2#</span><br><span style="color: hsl(0, 100%, 40%);">-        #  PcieRpClkSrcNumber:           Uses 2</span><br><span style="color: hsl(120, 100%, 40%);">+        #  PcieRpClkSrcNumber:           Uses 3</span><br><span>         #  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting</span><br><span>         #  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism</span><br><span>         register "PcieRpEnable[8]" = "1"</span><br><span>         register "PcieRpClkReqSupport[8]" = "1"</span><br><span>         register "PcieRpClkReqNumber[8]" = "2"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "PcieRpClkSrcNumber[8]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+        register "PcieRpClkSrcNumber[8]" = "3"</span><br><span>         register "PcieRpAdvancedErrorReporting[8]" = "1"</span><br><span>         register "PcieRpLtrEnable[8]" = "1"</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27536">change 27536</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27536"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1 </div>
<div style="display:none"> Gerrit-Change-Number: 27536 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Caveh Jalali <caveh@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>