[coreboot-gerrit] Change in coreboot[master]: This fix issus(202e7d4f3c)

[Xiang Wang (Code Review)]

Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/27543 )

Change subject: This fix issus(202e7d4f3c)
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This fix issus(202e7d4f3c)

When I tried to compile the RISC-V code, I found some errors:
     is undefined
    src/arch/riscv/timestamp.c does not exist
Currently RISC-V does not have the implementation and use of timestamp,
so I temporarily deleted the code related to timestamp in the Makefile.
And defined PRIu64.

Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/Makefile.inc
M src/arch/riscv/include/stdint.h
2 files changed, 4 insertions(+), 6 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27543/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6
Gerrit-Change-Number: 27543
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
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